Method of making a semiconductor memory device

Details Method of making a semiconductor memory device Method of making a semiconductor memory device

1994-09-01

1995-05-16

Thomas, Tom

Fishing, trapping, and vermin destroying

437 47, 437 60, 437919, H01L 2170

Patent

active

054160375

ABSTRACT:
In a DRAM which includes a memory cell consisting of one MOS transistor and one stacked capacitor, the node electrode of the capacitor is constituted of a stacked layer formed by alternately stacking a first conductor film and a second conductor film. As the first conductor film use is made of, for example, an n-type polycrystalline silicon film, and as the second conductor film use is made of, for example, an oxygen-rich n-type polycrystalline silicon film, or a silicide film of a high melting point metal. On the side faces of the node electrode, the edges of the first conductor films are at the positions that are more indented than the edges of the second conductor films. Because of the indentations, the surface area of the node electrode is increased so that a stacked capacitor with large capacitance can be realized even when the occupancy area of the capacitor is small. A node electrode with the above-mentioned structure can be formed by first anisotropically etching the stacked film, then by isotropically etching the film. This formation process is succinct, and the manufacturing process is also easy to handle.

REFERENCES:
patent: 4700457 (1987-10-01), Matsukawa
patent: 5021357 (1991-06-01), Taguchi et al.
Patent Abstracts of Japan, vol. 13, No. 359 (E-804) (3707), 10 Aug. 1989 & JP14 A-1 120 050 (Hitachi Ltd.), 12 May 1989.
Patent Abstracts of Japan, vol. 14, No. 151 (E-906) (4094), 22 Mar. 1990 & JP-A-2 010 762 (Mitsubishi Electric Corp.), 16 Jan. 1990.
IEDM 88, "3-Dimensional Stacked Capacitor Cell for 16M and 64M Drams", T. Ema et al., pp. 592-595 (1988).

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