Method of making a semiconductor device with capacitor element

Details Method of making a semiconductor device with capacitor element Method of making a semiconductor device with capacitor element

2002-06-20

2003-06-03

Niebling, John F. (Department: 2812)

Semiconductor device manufacturing: process

Having magnetic or ferroelectric component

C438S253000, C438S396000

Reexamination Certificate

active

06573111

ABSTRACT:

BACKGROUND OF THE INVENTION
1. Field of the Invention
The present invention relates to a semiconductor device having a MOS semiconductor device and a capacitor element which includes a capacitor film of a high dielectric material having a high dielectric constant or a ferroelectric material.
2. Description of the Related Art
A conventional semiconductor device
1000
and a method for producing the same will now be described.
FIG. 5
is a cross-sectional view illustrating the semiconductor device
1000
.
Referring to
FIG. 5
, a CMOS transistor
5
is formed on a silicon substrate
1
. The CMOS transistor
5
includes source and drain regions
2
and
3
, a gate insulating film
44
, and a gate
4
. The source and drain regions
2
and
3
and the gate
4
are each formed of silicon. A first insulating film
7
is formed over an oxide film
6
(which is formed on the silicon substrate
1
) and the CMOS transistor
5
. The first insulating film
7
has a layered structure including a silicon oxide film and a silicon nitride film.
A capacitor element
11
is formed in a predetermined location on the first insulating film
7
. The capacitor element
11
includes a lower electrode
8
and an upper electrode
9
, which are each formed of a platinum film, and a capacitor film
10
which is formed of an insulative metal oxide and is positioned between the lower electrode
8
and the upper electrode
9
. Platinum is employed as a material for the lower electrode
8
and the upper electrode
9
, because platinum does not react with the metal oxide contained in the capacitor film
10
even during a heat treatment and has a superior heat resistance.
A second insulating film
12
formed of a silicon oxide film is provided over the first insulating film
7
and the capacitor element
11
. Contact holes
13
are provided through the second insulating film
12
to the lower electrode
8
and the upper electrode
9
. Moreover, contact holes
14
are provided through the first insulating film
7
and the second insulating film
12
to the source and drain regions
2
and
3
. Although not shown in the drawing, another contact hole is provided to reach the gate
4
.
The CMOS transistor
5
and the capacitor element
11
are connected to each other by an interconnection layer
15
. The interconnection layer
15
is a multilayer film including a titanium layer, a titanium nitride layer, an aluminum layer and another titanium nitride layer in this order from the silicon substrate
1
. In the interconnection layer
15
, the titanium layer is provided closest to the silicon substrate
1
, or the CMOS transistor
5
, so as to allow titanium to diffuse into surfaces of the source and drain regions
2
and
3
and the gate
4
of the CMOS transistor
5
, thereby forming a low-resistance silicide in the surfaces.
Next, a method for producing the conventional semiconductor device
1000
will be described.
FIGS. 6A
to
6
E each illustrate a production step for producing the conventional semiconductor device
1000
.
First, as illustrated in
FIG. 6A
, the CMOS transistor
5
including the source and drain regions
2
and
3
and the gate
4
which are each formed of silicon are formed on the silicon substrate
1
. The gate
4
is actually provided over the gate insulating film
44
. Next, as illustrated in
FIG. 6B
, the first insulating film
7
is formed over the CMOS transistor
5
and the oxide film
6
which is formed on the silicon substrate
1
. A first platinum layer
8
a
, a ferroelectric film
10
a
, and a second platinum layer
9
a
are formed in this order on the first insulating film
7
. Then, the first platinum layer
8
a
, the ferroelectric film
10
a
, and the second platinum layer
9
a
are selectively etched to provide the capacitor element
11
having the lower electrode
8
, the capacitor film
10
and the upper electrode
9
, as illustrated in FIG.
6
C.
Next, as illustrated in
FIG. 6D
, the second insulating film
12
is formed to cover the first insulating film
7
and the capacitor element
11
, and the contact holes
13
are formed through the second insulating film
12
to the lower electrode
8
and the upper electrode
9
. Moreover, the contact holes
14
are formed through the second insulating film
12
and the first insulating film
7
to the source and drain regions
2
and
3
of the CMOS transistor
5
. Although not shown in the drawing, another contact hole is provided to reach the gate
4
.
Finally, as illustrated in
FIG. 6E
, in order to electrically connect the CMOS transistor
5
, the capacitor element
11
and other semiconductor elements (not shown) to one another, a titanium film, a titanium nitride film, an aluminum film and another titanium nitride film are formed in this order across the entire substrate, and this four-layer film is then selectively etched to form the interconnection layer
15
. Although not shown in the drawing, the interconnection layer
15
is also connected to the gate
4
. Subsequent processes are performed by an ordinary method to complete the semiconductor device
1000
.
SUMMARY OF THE INVENTION
A semiconductor device of the invention includes: a silicon substrate; a MOS semiconductor device provided on the silicon substrate, the MOS semiconductor device including a silicide region on an outermost surface thereof; a first insulating film covering the MOS semiconductor device; a capacitor element provided on the first insulating film, the capacitor element including a lower electrode, an upper electrode, and a capacitor film interposed between the lower, electrode and the upper electrode, and the capacitor film including a ferroelectric material; a second insulating film covering the first insulating film and the capacitor element; a contact hole provided in the first insulating film and the second insulating film over the MOS semiconductor device and the capacitor element; and an interconnection layer provided on the second insulating film for electrically connecting the MOS semiconductor device and the capacitor element to each other, wherein a bottom portion of the interconnection layer includes a conductive material other than titanium.
The silicide region may include one of a titanium silicide, a cobalt silicide, a chromium silicide, a molybdenum silicide, a tungsten silicide, a tantalum silicide, a palladium silicide, a platinum silicide, a vanadium silicide, and a zirconium silicide.
The interconnection layer may include one of a multilayer structure including a titanium nitride layer, an aluminum layer and a titanium nitride layer in this order from the silicon substrate; a multilayer structure including a tungsten nitride layer, an aluminum layer and a titanium nitride layer in this order from the silicon substrate; a multilayer structure including a tantalum nitride layer, an aluminum layer and a titanium nitride layer in this order from the silicon substrate; and a multilayer structure including a tungsten nitride layer, an aluminum layer and a titanium nitride layer in this order from the silicon substrate.
The upper electrode may include an iridium oxide layer.
Thus, the invention described herein makes possible the advantage of providing a semiconductor device in which a MOS semiconductor element and a capacitor element are electrically connected to each other with a low electric resistance therebetween using an interconnection layer without providing titanium in a bottom portion of the interconnection layer, thereby preventing deterioration of the characteristics of the capacitor element.
This and other advantages of the present invention will become apparent to those skilled in the art upon reading and understanding the following detailed description with reference to the accompanying figures.


REFERENCES:
patent: 5027185 (1991-06-01), Liauh
patent: 5053917 (1991-10-01), Miyasaka et al.
patent: 5475248 (1995-12-01), Takenaka
patent: 5566045 (1996-10-01), Summerfelt et al.
patent: 5648673 (1997-07-01), Yasuda
patent: 5883418 (1999-03-01), Kimura
patent: 0 503 078 (1992-09-01), None
patent: 0 690 507 (1996-01-01), None
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