Method of making a semiconductor device having protected edges

Details Method of making a semiconductor device having protected edges Method of making a semiconductor device having protected edges

1982-08-02

1985-02-19

Saba, William G.

Metal working

Method of mechanical manufacture

Assembling or joining

29576E, 148174, 148175, 148187, 148188, 357 34, 357 36, 357 59, H01L 2120, H01L 2904

Patent

active

044996578

ABSTRACT:
An n.sup.- silicon layer is epitaxially grown on an oxide film with predetermined openings disposed on one main face of an N.sup.+ silicon substrate to form single crystalline portions on the openings and polycrystalline portions on the oxide film. Ion implantation and thermal annealing is used to convert the polycrystalline portions to P.sup.+ external base regions and form P.sup.+ internal base regions in the single-crystalline portions. Arsenic ions are selectively implanted into the internal base regions to form n.sup.+ emitter regions. Then, base and emitter electrodes are formed on the external base and emitter regions to be electrically insulated from one another by an oxide film and a collector electrode is formed on the other main face of the substrate.

REFERENCES:
patent: 3189973 (1965-06-01), Edwards et al.
patent: 3600651 (1971-08-01), Duncan
patent: 3607466 (1971-09-01), Miyazaki
patent: 3611067 (1971-10-01), Oberlin et al.
patent: 4036672 (1977-07-01), Kobayashi
Sakai et al., "Elevated Electrode Integrated Circuits" IEEE Trans. Electron Dev., vol. ED-26, No. 4, Apr. 1979, pp. 379-385.
Okada et al., "New Polysilicon Process for Bipolar Device-PSA Technology" ibid, pp. 385-389.

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