Semiconductor device manufacturing: process – Packaging or treatment of packaged semiconductor
Reexamination Certificate
2001-06-20
2002-07-23
Niebling, John F. (Department: 2812)
Semiconductor device manufacturing: process
Packaging or treatment of packaged semiconductor
C438S121000
Reexamination Certificate
active
06423571
ABSTRACT:
TECHNICAL FIELD
The present invention relates to a semiconductor device used for high density packaging, multi-chip module, bare chip packaging, and the like, and a packaging structure of the semiconductor device.
BACKGROUND ART
In recent years, the reduced sizes and increased performances of the electronic devices will generate the demand for higher integration, higher density, and higher processing speed of semiconductor devices used for the electronic devices. To meet such a demand, packages of semiconductor devices are being developed from a pin insertion type to a surface packaging type for increasing the packaging densities, and also developed from a DIP (Dual Inline Package) type to a QFP (Quad Flat Package) type and a PGA (Pin Grid Array) type for coping with the multi-pin arrangement.
Of the packages thus developed, the QFP is difficult to cope with the multi-pin arrangement because it is so configured that leads to be connected to a packaging substrate are concentrated only at a peripheral portion of the package and are also liable to be deformed due to finer diameters thereof. Besides, the PGA has a limitation in coping with both high speed processing and surface packaging because it is so configured that terminals to be connected to a packaging substrate are elongated and very collectively arranged.
Recently, to solve these problems and to realize a semiconductor device capable of coping with high speed processing, a BGA (Ball Grid Array) package is disclosed in U.S. Pat. No. 5,148,265, which has ball-like connection terminals over the entire packaging surface of a carrier substrate electrically connected to a semiconductor chip by gold wire bonding. In this package, since the terminals to be connected to a packaging substrate are formed into ball-like shapes, they can be arranged in a dispersed manner over the entire packaging surface without such deformation of leads as found in the QFP, so that pitches between the terminals become larger, to thereby make surface packaging easy; and also since the lengths of the connection terminals are shorter than those of the PGA, an inductance component becomes smaller and thereby a signal transmission speed becomes faster, with a result that such a package is allowed to cope with high speed processing.
In the above-described BGA package, an elastic body is inserted as an interposer between a semiconductor chip and terminals of a packaging substrate for relieving a thermal stress produced due to a difference in thermal expansion between the packaging substrate and the semiconductor chip upon packaging thereof. The semiconductor device having such a structure, however, has problems depending on the use of gold wire bonding for connection with upper electrodes of the semiconductor chip; namely, since the connection portions connected to the gold wires are concentrated only at a peripheral portion of the chip, the structure has a spontaneous limitation in coping with the further increasing futuristic demand for multi-pin arrangement and higher processing speed of semiconductor devices and has also an inconvenience in terms of mass-production and improvement in production yield because of the increased number of production steps due to the complexity thereof.
Japanese Patent Laid-open No. Hei 5-326625 discloses an improved packaging structure of a flip-chip type package in which a LSI chip having solder bumps is mounted on a multi-layered wiring ceramic substrate having solder bumps, wherein a sealing member is filled between the LSI chip and the multi-layered wiring ceramic substrate as a carrier substrate. The above packaging structure, however, seems to have a problem in terms of higher density interconnection, higher response speed of signals, and miniaturization of the package, because the use of the ceramic substrate as multiple wiring layers makes it difficult to reduce a dielectric constant. Another problem of such a package resides in the production step requiring high temperature burning for ceramic, and in difficult handling of the brittle, thin ceramic substrate.
Objects of the present invention are to provide a semiconductor device capable of coping with the further increasing futuristic demand for high speed processing and high density packaging and being high in reliability in connection with a packaging substrate; and to provide a packaging structure of the semiconductor device.
DISCLOSURE OF THE INVENTION
The gist of the present invention made for solving the above-described problems is as follows:
(1) According to the present invention, there is provided a semiconductor device including: a multi-layered wiring structure having a conductive layer to be electrically connected to a packaging substrate, the structure being provided on the surface of a semiconductor chip on the packaging substrate side; and ball-like terminals disposed in a grid array on the surface of the multi-layered wiring structure on the packaging substrate side, wherein the multi-layered wiring structure includes a buffer layer for relieving a thermal stress produced between the semiconductor chip and the packaging substrate after packaging thereof, and multiple wiring layers.
(2) According to the present invention, there is also provided a semiconductor device including: a multi-layered wiring structure having a conductive layer to be electrically connected to a packaging substrate, the structure being provided on the surface of a semiconductor chip on the packaging substrate side; and ball-like terminals disposed in a grid array on the surface of the multi-layered wiring structure on the packaging substrate side, wherein an interlayer insulating film in multiple wiring layers for transmitting an electric signal of the multi-layered wiring structure is made of a material for reliving a thermal stress produced between the semiconductor chip and the packaging substrate after packaging thereof.
(3) According to the present invention, there is also provided a packaging structure connected to and mounted on the packaging substrate via the ball-like terminals disposed in a grid array.
The above-described multi-layered wiring structure is required to attain two purposes: to achieve electric connection between the semiconductor device and a packaging substrate when the semiconductor device is mounted on the packaging substrate; and to relieve a thermal stress produced between the semiconductor device and the packaging substrate upon packaging thereof. Accordingly, the features of the present invention reside in that
{circle around (1)} the above multi-layered wiring structure includes two components, that is, multiple wiring layers for transmitting an electric signal and a buffer layer for relieving a thermal stress; or
{circle around (2)} an interlayer insulating film in multiple wiring layers for transmitting an electric signal of the multi-layered wiring structure is made of a material for reliving a thermal stress produced between a semiconductor chip and a packaging substrate after packaging thereof, whereby serving as the function of the buffer layer.
The above multi-layered wiring structure is preferably composed of three or more layers including a conductive layer portion having a ground layer, power supply layer, and wiring layer. This makes it possible to increase a signal transmission speed and to reduce the occurrence of noise.
Each of the buffer layer and the insulating layer is preferably made of a material having a low dielectric constant.
FIG. 1
shows a relationship between the dielectric constant and each of the thickness of the insulating layer and the transmission delay time. In addition, the film thickness h of the insulating layer is given by the following equation [1]. For example, for the wiring having a width w=50 &mgr;m and a height t=30 &mgr;m, the film thickness h at a characteristic impedance Z
0
=55 &OHgr; can be calculated by substituting these values in the equation [1].
The delay time Td can be given by substituting a dielectric constant &egr;
r
of the insulating layer in th
Akahoshi Haruo
Anjou Ichirou
Eguchi Shuji
Ishii Toshiaki
Miwa Takao
Antonelli Terry Stout & Kraus LLP
Hitachi , Ltd.
Jones Josetta I.
Niebling John F.
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