Method of making a semiconductor device comprising lower and upp

Details Method of making a semiconductor device comprising lower and upp Method of making a semiconductor device comprising lower and upp

1994-03-08

1995-05-02

Thomas, Tom

Fishing, trapping, and vermin destroying

437 47, 437 52, 437919, H01L 2170

Patent

active

054119120

ABSTRACT:
In a semiconductor device comprising charge storage capacitors, each of which comprises a patterned electrode having electrode side and top surfaces, a dielectric film (22) on the side and top surfaces, and a covering electrode (23) on the dielectric film, the patterned electrode is composed of a lower silicon layer (26) having layer side and top surfaces and an upper silicon layer (27) lying on the layer side and top surfaces and having the electrode side and top surfaces. The dielectric film may be in direct contact with the electrode side and top surfaces. In this event, the lower silicon layer is preferably doped to a lower concentration between 10.sup.15 and 10.sup.18 atoms per cubic centimeter and the upper silicon layer, to a higher concentration between 10.sup.18 and 10.sup.20 atoms per cubic centimeter. Alternatively, a barrier metal film may be interposed between the dielectric film and the electrode side and top surfaces. In this event, each of the lower and the upper silicon layers is preferably doped to the lower concentration. More preferably, an amorphous silicon film is preliminarily deposited on micro-rough side and top surfaces of an underlying silicon layer to provide the upper silicon layer having smooth electrode side and top surfaces.

REFERENCES:
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patent: 4970564 (1990-11-01), Kimura et al.
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Mitsumasa Koyanagi et al., "A 5-V Only 16-kbit Stacked-Capacitor MOS RAM," IEEE Transactions on Electron Devices, vol. ED-27, No. 8, Aug. 1980, pp. 1596-1601.
T. Ema et al., "3-Dimensional Stacked Capacitor Cell for 16M and 64M DRAMS," IEDM Tech. Dig., 1988, pp. 592-595.
W. Wakamiya et al., "Novel Stacked Capacitor Cell for 64Mb DRAM," VLSI Symp., 1989, pp. 69-70.
"Self-Aligned Polycide Bit Line Structure," IBM Technical Disclosure Bulletin, vol. 30, No. 12, May 1988, pp. 109-110.

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