Method of making a parylene coating for soldermask

Details Method of making a parylene coating for soldermask Method of making a parylene coating for soldermask

2002-05-22

2003-10-21

Niebling, John F. (Department: 2812)

Semiconductor device manufacturing: process

Packaging or treatment of packaged semiconductor

Assembly of plural semiconductive substrates each possessing...

C438S110000, C438S129000, C438S598000, C438S599000, C438S612000, C438S613000, C438S618000

Reexamination Certificate

active

06635510

ABSTRACT:

FIELD OF THE INVENTION
This invention relates to methods for fabrication of High Density Interconnect (HDI) circuits, and more particularly, to such methods for making an HDI circuit including rear surface (backside) connections by using parylene both as a protective coating and as a mask.
BACKGROUND OF THE INVENTION
In general, HDI structures allow the interconnection of relatively large numbers of integrated-circuit chips into complex systems in a cost-effective manner. HDI circuits are formed by mounting two or more semiconductor or solid state chips with electrodes or bonding pad sites so that those surfaces of the chip having electrodes are coplanar on a layer of transparent dielectric material, for example, polyimide. The electrode or bonding pad site is disposed adjacent the dielectric material. The opposite side of the chip may also include a rear surface (backside) connection. Thereafter, a laser is optically aligned to the position of each chip at the locations of the electrode to drill through via holes through the dielectric material. An interconnect or metallization layer(s), with a first layer possibly including titanium and a second layer including copper, is then deposited over the polyimide layer and extends into the via holes to make electrical contact to the electrode or pad disposed thereunder. The metallization layer may be patterned to form individual conductors during the deposition process or may be deposited as a continuous layer, and then patterned using photoresist and etching. Additional dielectric layers for isolation between the first metallization layer and subsequent metallization layers may be added to the substrate.
As mentioned, some chips used in an HDI context have rear-surface connections as well as front-surface connections. The rear surface connections may be used for electrical or thermal conduction, or both. The processing of HDI structures for applying the front side interconnects often involves vacuum processes, lasering, and harsh or corrosive chemicals which may adversely affect the backside connections.
Methods for providing protection to the backsides of HDI structures and printed circuit boards from the harsh chemicals involved in processing the structures was provided in the prior art by application of plater's tape onto the metallized back of the process carrier prior to processing. The protective plater's tape must subsequently be removed prior to vacuum processes, including sputter reactive ion etching (RIE), to prevent outgassing. In a multi-layer module manufacturing process, the taping and untaping process can be repeated as many as forty times. The repetition of these taping and untaping steps is expensive, and can result in handling and particulate damage to the HDI interconnect circuitry. In addition to the added labor costs, the seal formed by the plater's tape may not be perfectly effective in preventing leaks through which chemicals may enter and adversely affect the circuitry.
Improved HDI manufacturing is desired.
SUMMARY OF THE INVENTION
Briefly described, a method for making an HDI circuit including backside connections by using parylene as a protective coating includes the steps of: procuring an insulating substrate defining front and rear surfaces and including an active chip essentially coplanar with the insulating substrate, which active chip has electrical connections on a front surface of the chip facing the rear surface of the substrate and which also has at least one of a thermal and electrical connection exposed on a rear surface of the chip, applying a parylene coating to the at least one connection on the rear surface of the chip, to thereby protect the at least one connection; performing additional HDI interconnect processing steps on the front surface of the substrate, including at least via forming, patterning, and metal deposition, which in the absence of the parylene coating may adversely affect the at least one connection; after the step of performing additional HDI front surface interconnect processing steps, selectively removing a portion of the parylene coating in the region of the at least one connection to thereby expose at least a portion of the at least one connection in a selected connection region; and making electrical connection to the at least one connection by application of a conductive material in its liquid state to the selected region, whereby the parylene coating limits the application of the conductive material to the exposed region. The step of making electrical connection to the at least one connection is performed by application of solder or conductive epoxy in its liquid state. The step of selectively removing a portion of the parylene coating is performed by a scanned laser, and more particularly, a KrF excimer laser. The parylene coating may comprise monochloropolyparaxylylene.


REFERENCES:
patent: 5373627 (1994-12-01), Grebe
patent: 6184121 (2001-02-01), Buchwalter et al.
patent: 6255137 (2001-07-01), Gorczyca et al.

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