Metal working – Barrier layer or semiconductor device making – Barrier layer device making
Reexamination Certificate
2002-01-09
2003-02-25
Nguyen, Ha Tran (Department: 2812)
Metal working
Barrier layer or semiconductor device making
Barrier layer device making
C361S301300, C361S306300, C427S079000
Reexamination Certificate
active
06524352
ABSTRACT:
TECHNICAL FIELD
The present invention relates generally to printed circuit boards, and more particularly to a laminate structure capable of being used in such circuit boards as an internal capacitor member. The invention also relates to possible utilization of such a resulting circuit board structure as an interposer for coupling circuitized structures, including, for example, other circuit boards, modules, etc.
BACKGROUND OF THE INVENTION
Mounting electrical components such as discrete resistors, discrete capacitors, transistors, digital circuits, etc. on printed circuit boards (PCBs) is well known. It is common for such a PCB to contain many layers. Typically, most of the components are mounted on the surface. Some of the conductors used to interconnect the components may also be printed on the surface. The inner layers are primarily used to interconnect the components through other conductors printed on these inner layers and conductive vias passing through the outer and inner layers. For complex circuits, the surface area must be carefully allocated to fit the many requisite components. Also, in the case of capacitor components, it is desirable to position some of the capacitors near other, associated components to minimize path length and thereby minimize parasitic inductance.
It is known to form a discrete capacitor from a bottom aluminum electrode, a next layer of tantalum (Ta), a next layer of Ta
2
O
5
serving as a dielectric, and a top electrode layer. This capacitor may be mounted on the surface of a PCB, and two conductive vias passed through the PCB to connect to the two electrodes. This capacitor was not part of a printed circuit board, but instead was a surface component on a substrate.
Conserving precious space on a PCB's outer surfaces make it desirable to form some of the capacitors within the printed circuit board. Doing so will reduce demands on the surface area and still permit a capacitor to be located near an associated component, assuming no space is available on the surface near this component.
Various techniques are known to form a capacitor within a printed circuit board. See for example, U.S. Pat. Nos. 5,079,609, 5,161,086, Japanese laid-open utility model 62-166616 (OCT. 22, 1987), IBM Technical Disclosure Bulletin (TDB) Vol. 22, No. 6 (11/79) at p. 2261, U.S. Pat. Nos. 5,155,655 and 5,261,153. While these techniques may be effective in their respective printed circuit boards and for their respective applications, further improvements are desirable to provide a high amount of capacitance per amount of inner layer area utilized, provide a fabrication process with acceptable cost and complexity and provide a fabrication process which is compatible with the requisite printed circuit board dielectric materials, such as epoxy, polyimide or Teflon polymers and polymer impregnated glass cloth or fiber laminate materials and the like. Epoxy resins typically have glass transition temperatures from about 120° C. to about 190° C. and thermal decomposition temperatures from about 300° C. to about 375° C. Epoxy resins will withstand short duration exposures above the glass transition temperature, but will not withstand temperatures excursions above the thermal decomposition temperature. For example, the fabrication process required for the capacitor cannot require so much heat or harsh chemicals as to degrade the printed circuit board other materials.
In U.S. Pat. Nos. 5,745,334 and 5,972,053, there is defined a PCB having an internal capacitor using tantalum (Ta) or hafnium (Hf) to form a single capacitor which is then laminated up with an organic dielectric material (e.g., epoxy resin) and other desired conductive and dielectric layers to form a multilayered PCB. Oxides of one of these metals are also formed in the underlying Ta or Hf layer prior to the aforementioned subsequent lamination.
To provide an end product with significantly greater operational capabilities, a parallel capacitor has been produced according to the teachings of the present invention which includes the advantages obtainable using Ta or Hf, while still overcoming the disadvantages associated with the structures described in the documents described above prior to U.S. Pat. Nos. 5,745,334 and 5,972,053.
It is believed that such a parallel capacitor usable within a multilayered PCB will constitute a significant advancement in the art. It is further believed that use for such a PCB as an interposer between two circuitized structures would represent a further art advancement.
OBJECTS AND SUMMARY OF THE INVENTION
It is a primary object of the invention to provide an enhanced capacitor laminate which can be successfully utilized in various electronic packaging and the like applications.
It is another object of the invention to provide a method of making such a capacitor which can be made using many conventional processes, thus reducing the costs for such a product.
According to one aspect of the invention, there is provided a parallel capacitor laminate comprising a first electrically conductive layer having first and second opposing surfaces, first and second layers of electrically conductive material located on the first and second opposing surfaces of the first conductive layer, respectively, first and second layers of inorganic dielectric material located on the first and second layers of the electrically conductive material, respectively, and third and fourth layers of electrically conductive material located on the first and second layers of inorganic dielectric material, respectively. The third and fourth electrically conductive layers form the outer conductive layers of a substantially parallel capacitor with the first and second electrically conductive layers.
According to another aspect of the invention, there is provided a method of making a parallel capacitor laminate comprising providing a first electrically conductive layer having first and second opposing surfaces, forming first and second layers of electrically conductive material on the first and second opposing surfaces of the first conductive layer, respectively, forming first and second layers of inorganic dielectric material on the first and second layers of the electrically conductive material, respectively, and forming third and fourth layers of electrically conductive material on the first and second layers of inorganic dielectric material, respectively. The first and second electrically conductive layers form a substantially parallel capacitor with the third and fourth electrically conductive layers.
REFERENCES:
patent: 3699011 (1972-10-01), Nishimura
patent: 4460938 (1984-07-01), Clei
patent: 4749449 (1988-06-01), Scott
patent: 4996097 (1991-02-01), Fischer
patent: 5027253 (1991-06-01), Lauffer et al.
patent: 5065284 (1991-11-01), Hernandez
patent: 5079609 (1992-01-01), Takagi
patent: 5155655 (1992-10-01), Howard et al.
patent: 5161086 (1992-11-01), Howard et al.
patent: 5172304 (1992-12-01), Ozawa et al.
patent: 5261153 (1993-11-01), Lucas
patent: 5745333 (1998-04-01), Frankeny et al.
patent: 5745334 (1998-04-01), Hoffarth et al.
patent: 5796587 (1998-08-01), Lauffer et al.
patent: 5972053 (1999-10-01), Hoffarth et al.
patent: 6343001 (2002-01-01), Japp et al.
patent: 62-166616 (1987-10-01), None
IBM Technical Disclosure Bulletin, vol. 22, No. 6, 11/79, “Raw Card Composite Capacitor”, by Olsen.
“Thin Film Materials Research”, Emmanuel P. Giannelis, Materials Science And Engineering, Nov., 1993.
“Spin-On Films Add New Dimension to ULSI Circuits”, Giannelis et al, Circuits & Devices, Nov., 1993.
Adae-Amoakoh Sylvia
Lauffer John M.
Lowell Michael D.
Markovich Voya R.
Sniezek Joseph J.
Fraley Lawrence R.
Nguyen Ha Tran
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