Method of making a nonvolatile memory array having cells with se

Details Method of making a nonvolatile memory array having cells with se Method of making a nonvolatile memory array having cells with se

1990-09-28

1991-09-03

Hearn, Brian E.

Fishing, trapping, and vermin destroying

437 43, 437 48, 437 40, 437 50, 437193, H01L 2170

Patent

active

050454919

ABSTRACT:
A nonvolatile memory cell having separate regions for programming and erasing. The cells are formed in an array at a face of a semiconductor body, each cell including a source that is part of a source-column line and including a drain that is part of a drain-column line. Each cell has first and second sub-channels between source and drain. The conductivity of the first sub-channel of each cell is controlled by a field-plate, which is part of a field-plate-column line, positioned over and insulated from the first sub-channel. The conductivity of each of the second sub-channels is controlled by a floating gate formed over and insulated from the second sub-channel. Each floating gate has a first tunnelling window positioned over the adjacent source-column line and has a second tunnelling window positioned over the adjacent drain-column line. Row lines, including control gates, are positioned above and insulated from the floating gates of the cells for reading, programming and erasing the cells. The field-plate conductor permits programming of the cells through the first tunnelling window only and erasing of the cells through the second tunnelling window only, or vice versa.

REFERENCES:
patent: 4822750 (1989-04-01), Perlegos et al.
patent: 4833096 (1989-05-01), Huang et al.
patent: 4853895 (1989-08-01), Mitchell et al.
patent: 4924437 (1990-05-01), Paterson et al.
patent: 4980309 (1990-12-01), Mitchell et al.
patent: 4994403 (1991-02-01), Gill

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