Method of making a non-volatile memory cell utilizing polycrysta

Fishing – trapping – and vermin destroying

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437195, 437978, 437979, H01L 2176, H01L 21265

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active

051089394

ABSTRACT:
A method and structure for forming in an EEPROM memory transistor a tunnel dielectric region having an extremely small surface area. A floating gate region is formed in the conventional manner above a gate dielectric layer. The drain region is exposed utilizing photolithographic techniques and the gate dielectric removed therefrom. A thin layer of tunnel dielectric is then formed on the exposed drain region. A thin layer of polycrystalline silicon is then formed and etched in order to create very narrow floating gate extensions of polycrystalline silicon along the edge of the previously formed floating gate. The floating gate extension formed in this manner which overlies the drain region is separated from the drain region by thin tunnel dielectric. A dielectric is then formed on the device in order to provide a dielectric over the drain region which has a greater thickness than the tunnel dielectric underlying the floating gate extension.

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patent: 4812885 (1989-03-01), Riemenschneider
patent: 4822750 (1989-04-01), Perlegos et al.
patent: 4931847 (1990-06-01), Corda
patent: 5019879 (1991-05-01), Chiu
patent: 5021848 (1991-06-01), Chiu
"A 16KB Electrically Erasable Nonvolatile Memory" by W. Johnson et al., 1980 IEEE International Solid-State Circuits Conference, p. 152.

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