Method of making a MOS device with drain side channel implant

Details Method of making a MOS device with drain side channel implant Method of making a MOS device with drain side channel implant

1993-12-10

1995-06-27

Hearn, Brian E.

Fishing, trapping, and vermin destroying

437 43, 437984, H01L 21266

Patent

active

054279631

ABSTRACT:
An MOS device is provided having a drain- or source-side implant into the channel region in order to minimize short-channel effects. Implant into the channel region is achieved using conventional processing techniques, wherein the channel implant is directed substantially perpendicular to the upper surface of the substrate. Numerous masking steps and reorientation of the substrate is not needed. Additionally, the drain- or source-side implant mask can be formed from currently existing masks and incorporated into a standard processing flow for either a standard MOS device or a memory array comprising dual-level polysilicon. If drain-side implant is chosen, then the lateral demarcation line between the drain implant and the substrate is preferably placed within the channel region, and preferably near a mid-point within the channel a spaced distance below a subsequently placed, overlying polysilicon.

REFERENCES:
patent: 4999812 (1991-03-01), Amin
patent: 5070032 (1991-12-01), Yuan et al.
patent: 5100818 (1992-03-01), Arima et al.
patent: 5101250 (1992-03-01), Arima et al.
patent: 5120671 (1992-06-01), Tang et al.
patent: 5304505 (1994-04-01), Hazani
patent: 5316961 (1994-05-01), Okazawa
K. Robinson, "Endurance Brightens the Future of Flash--Flash Memory as a Viable Mask-Storage Alternative", Electronic Component News, (Nov., 1988), pp. 167-169.
S. Lai et al., "Comparison and Trends in Today's Dominant E.sup.2 Technologies", Int'l Electron Devices Meeting Tech. Digest, pp. 580-583 (1986).
B. J. Woo et al., "A Novel Memory Cell Using Flash Array Contactless EPROM (FACE) Technology", IEDM, pp. 91-94 (1990).
O. Bellezza et al., "A New Self-Aligned Field Oxide Cell for Multimegabit EPROMs", IEDM, pp. 579-582 (1989).
Yosiaki S. Hisamune et al., "A 3.6 .mu.m.sup.2 Memory Cell Structure for 16MB EPROMs", pp. 583-586 (1989).

Affiliated with

Also associated with

Rating

Method of making a MOS device with drain side channel implant does not yet have a rating. At this time, there are no reviews or comments for this patent.

If you have personal experience with Method of making a MOS device with drain side channel implant, we encourage you to share that experience with our LandOfFree.com community. Your opinion is very important and Method of making a MOS device with drain side channel implant will most certainly appreciate the feedback.

Rate now

Comments { 0 }

Profile ID: LFUS-PAI-O-286908