Metal working – Method of mechanical manufacture – Electrical device making
Reexamination Certificate
2001-07-27
2004-01-20
Arbes, Carl J. (Department: 3729)
Metal working
Method of mechanical manufacture
Electrical device making
C029S846000, C029S835000, C029S848000, C029S852000, C174S254000
Reexamination Certificate
active
06678952
ABSTRACT:
FIELD OF THE INVENTION
The present invention relates to methods of making microelectronic packages, and to methods of making microelectronic components for use in fabrication of microelectronic packages.
BACKGROUND OF THE INVENTION
Microelectronic elements, such as semiconductor chips, are typically incorporated in a microelectronic package having terminals for forming electrical connections between the semiconductor chip and a second microelectronic element. Methods of making a microelectronic package typically include assembling the semiconductor chip with a microelectronic component. The microelectronic component incorporates conductive features for connecting with contacts on the semiconductor chip and for connecting with the second microelectronic element.
The microelectronic component may comprise a dielectric layer including conductive features on both of the two major surfaces of the dielectric layer. Vias, which comprise holes that extend from one major surface to another major surface of the dielectric layer, are typically used to form electrical connections between features on each major surface.
After a via is formed in a dielectric layer, the vias are bounded by walls of the dielectric layer. The vias are lined with an electrically conductive material so that the conductive features on one major surface are electrically connected to conductive features on the other major surface. To line the vias with conductive material, the vias are first “seeded” by lining the vias with a small amount of electrically conductive material so as to cover the dielectric walls of the via. Additional electrically conductive material can then be electroplated onto the seeded vias. After the vias are lined, terminals for connecting to the second microelectronic element are formed in contact with the vias. Lining the vias by seeding the vias and then electroplating conductive material in the vias is time consuming and expensive.
Components having conductive features on two sides, or “two metal components,” are typically made by forming conductive features on one side of the component separately from the conductive features on the other side of the component. A two metal component may be formed from a dielectric layer having a layer of metal on each of the major surfaces of the dielectric layer. Photolithographic techniques are used to form the conductive features on both sides of the dielectric layer. The conductive features on one side of the dielectric layer are formed before the vias are formed. After vias are formed, the vias are lined and then the conductive features on the other side of the dielectric layer are formed. Multiple steps are required in forming the conductive features from the top metal layer, forming and lining the vias, and forming conductive features from the bottom metal layer separately.
Further improvements in forming microelectronic components and microelectronic packages are desired.
SUMMARY OF THE INVENTION
In a first aspect of the present invention, a method of forming a microelectronic element comprises providing a dielectric layer with a top side, a bottom side, a top metal layer on the top side, and a bottom metal layer on the bottom side. First apertures are formed in the top metal layer and vias are formed in the dielectric layer so that the vias are aligned with the first apertures. A first resist is applied to the top metal layer and a second resist is applied to the bottom metal layer. The first resist and second resist are patterned in the same step to form first openings in the first resist and second openings in the second resist. The first openings leave uncovered portions of the top metal layer surrounding the vias, and the second openings are aligned with the first openings. Top conductive features are formed from portions of the top metal layer aligned with said first openings and bottom conductive features are formed on portions of the bottom metal layer aligned with said second openings. The top conductive features and the bottom conductive features are electrically interconnected through the vias by depositing an electrically conductive material in the vias without seeding the vias.
Thus, the resists are patterned in the same step to simplify the method and require less time in forming conductive features on the top and bottom sides of a component. In addition, vias are formed to interconnect the top conductive features and bottom conductive features. Electrically conductive material is deposited in the vias to interconnect the top conductive features and bottom conductive features, without first lining the vias.
In certain preferred embodiments, the step of forming first apertures is performed before applying a first resist and applying a second resist. The step of patterning the first resist and second resist preferably comprises photolithographically patterning the first resist and second resist. The step of patterning preferably comprises exposing the first resist and second resist in the same step and then developing the first resist and the second resist in the same step. Such patterning of the first resist and second resist greatly simplifies the method.
The top conductive features may have a number of shapes. For example, the top conductive features may be formed as annular features surrounding the vias.
The conductive features may be formed by removing metal from the top metal layer, the bottom metal layer or both. The conductive features may also be formed by adding metal to the top metal layer, the bottom metal layer or both. In certain preferred embodiments, the step of forming the bottom conductive features includes depositing a first metal in the second openings of the second resist.
In certain preferred embodiments, a second metal is added on the first metal deposited in the second openings of the second resist. The second metal may also be added on the top metal layer, on the portions of the top metal layer left uncovered by the first openings. The step of forming top conductive features and bottom conductive features may comprise removing metal from portions of the top metal layer and the bottom metal layer that are left uncovered by the second metal. Thus, the second metal is utilized in forming the top conductive features and bottom conductive features. Preferably, the second metal is added on the top metal layer and bottom metal layer in the same step, further simplifying the method.
The second metal preferably has different etching characteristics than the etching characteristics of the top metal layer and the bottom metal layer. Metal may be removed from the top metal layer and the bottom metal layer by etching. For example, the first metal may comprise copper and the second metal may comprise gold. The top metal layer and the bottom metal layer may also comprise layers of copper.
In certain preferred embodiments, a third resist is applied, covering the second metal and the bottom metal layer. The third resist is patterned to form third openings in the third resist. The third openings uncover a portion of the second metal deposited on the first metal. Second metal is deposited in the third openings to form pads for the bottom conductive features.
In certain preferred embodiments, the step of forming first apertures in the top metal layer comprises applying a third resist on the top metal layer, patterning the third resist to form third openings, and removing metal from portions of the top metal layer left uncovered in the third openings. The step of forming vias may comprise cutting through the dielectric layer at the first apertures.
In another aspect of the present invention, a method of making a microelectronic package comprises providing a dielectric layer having a top side and a bottom side. A top conductive feature is formed on the top side of the dielectric layer and a bottom conductive feature is formed on the bottom side of the dielectric layer. The dielectric layer is juxtaposed with at least one microelectronic element having contacts. The contacts of the microelectronic element are bonded with the bottom c
Arbes Carl J.
Lerner David Littenberg Krumholz & Mentlik LLP
Phan Thiem Duh
Tessera Inc.
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