Method of making a microelectronic package

Metal working – Method of mechanical manufacture – Electrical device making

Reexamination Certificate

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Details

C029S832000, C029S834000, C029S844000, C029S847000, C174S262000, C257S684000, C361S769000

Reexamination Certificate

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10728306

ABSTRACT:
A microelectronic element is formed from a structure including metal layers on top and bottom sides of a dielectric. Apertures are formed in the top metal layer, and vias are formed in the dielectric in alignment with the apertures. Top and bottom conductive features are formed in proximity to the vias, as by selectively depositing a metal on the metal layers or selectively etching the metal layers. The top and bottom conductive features are connected to one another by depositing a conductive material into the vias, most preferably without seeding the vias as, for example, by depositing solder in the vias.

REFERENCES:
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patent: 4935584 (1990-06-01), Boggs
patent: 5021129 (1991-06-01), Arbach et al.
patent: 5404637 (1995-04-01), Kawakami
patent: 5886409 (1999-03-01), Ishino et al.
patent: 6051093 (2000-04-01), Tsukahara
patent: 6200143 (2001-03-01), Haba et al.
patent: 6222136 (2001-04-01), Appelt et al.
patent: 6252779 (2001-06-01), Pierson et al.

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