Method of making a lead on chip (LOC) semiconductor device

Details Method of making a lead on chip (LOC) semiconductor device Method of making a lead on chip (LOC) semiconductor device

1994-10-19

1996-07-16

Vo, Peter

Metal working

Method of mechanical manufacture

Electrical device making

29841, 174 524, 437217, 437220, H01R 4300, H01L 2160

Patent

active

055355099

ABSTRACT:
A semiconductor device including a lead on chip structure employs two frames. One of the frames includes a die pad and an outer frame portion and the other frame includes a plurality of leads and an outer lead portion. After a semiconductor chip is die bonded to the die pad, the two frames are connected to each other with the leads extending across the semiconductor chip. Slits within the second frame provide access to parts of the outer frame of the first frame and the first frame is severed at those slits. The severed portions of the first frame are removed after which the leads of the second frame are connected by wire bonding to the semiconductor chip. Finally, the semiconductor chip, the remaining part of the first frame, and the second frame are encapsulated in a resin with leads extending from the resin. The remaining parts of the outer frame of the second frame are removed by cutting and the exposed leads outside the resin are formed into a desired shape.

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patent: 4791473 (1988-12-01), Phy
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patent: 5089439 (1992-02-01), Lippey
patent: 5188982 (1993-02-01), Huang
patent: 5218229 (1993-06-01), Farnworth
patent: 5293066 (1994-03-01), Tsumura
patent: 5339518 (1994-08-01), Tran et al.
IBM Technical Disclosure Bulletin, vol. 15, No. 12 May 1973.

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