Method of making a lead-free integrated circuit package

Details Method of making a lead-free integrated circuit package Method of making a lead-free integrated circuit package

2005-05-10

2005-05-10

Arbes, Carl J. (Department: 3729)

Metal working

Method of mechanical manufacture

Electrical device making

C029S832000, C029S837000, C029S746000, C029S852000, C029S854000, C029S855000, C029S856000, C427S096400, C427S097100, C427S098300, C438S126000, C438S613000, C438S614000

Reexamination Certificate

active

06889429

ABSTRACT:
An integrated circuit package (60) has a substrate (12) with a first surface (51) for mounting a semiconductor die (20) and a second surface (52) defining a via (70). A lead (26) is formed by plating a conductive material to project outwardly from the second surface. The conductive material extends from the lead through the first via for coupling to the semiconductor die.

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patent: 5808873 (1998-09-01), Celaya et al.
patent: 5895229 (1999-04-01), Carney et al.
patent: 6046499 (2000-04-01), Yano et al.
patent: 6162664 (2000-12-01), Kim
patent: 6262477 (2001-07-01), Mahulikar et al.

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