Fishing – trapping – and vermin destroying
Patent
1987-08-31
1989-06-06
Hearn, Brian E.
Fishing, trapping, and vermin destroying
437 34, 437 57, 437160, 437104, H01L 21265
Patent
active
048371793
DESCRIPTION:
BRIEF SUMMARY
TECHNICAL FIELD
The present invention concerns improvements in or relating to the manufacture of Metal-Oxide-Semiconductor Field-Effect (MOS) transistors, and in particular but not exclusively, NMOS/PMOS compatible methods for CMOS circuit processing.
For small (.ltoreq.1.5 .mu.m) channel length transistors, a lightly doped drain structure is highly desirable. For this range of channel lengths NMOS transistors, in particular, are susceptible to threshold--voltage and gain instabilities (hot-electron effects) due to high electric fields. Electric fields in the vicinity of the drain diffusion can be much reduced by tailoring the drain dopant profile--ie. by adopting a lightly doped drain structure.
BACKGROUND ART
In a conventional process two implant steps are used to provide the lightly doped drain structure. Usually this process comprises a heavy implant of phosphorus followed by a light implant of arsenic into silicon. Here, however, after annealing, the junction depth is deep, typically greater than 0.5 .mu.m. It is a problem that these deep junctions degrade small channel length transistor performance, and such structures often prove to be unreliable.
DISCLOSURE OF THE INVENTION
The invention provides a method for MOS transistor manufacture, a simple and alternative method that affords shallow junction structure and thus avoids the problem just discussed.
In accordance with the invention there is thus provided a method for MOS transistor manufacture comprising essentially the following steps:
firstly, defining on a silicon crystal substrate a gate oxide and gate electrode;
secondly, applying to the gate oxide and gate electrode a deposit of dielectric material incorporating a quantity of n-type dopant, and etching same to create a narrow sidewall;
thirdly, introducing a heavy implant dose of appropriate dopant species, to produce a shallow implant adjacent to the side of the sidewall; and,
fourthly, annealing to regrow the silicon crystal and to activate the implanted dopant.
The method aforesaid requires no additional implantation. An implant step has thus been obviated. Instead, doped dielectric material has been used and the transistor manufacture process simplified. The action of the light implant comes from the doped dielectric. This adds dopant to the drain (and also the source) on the channel side of the drain (source). The addition of this light diffusion tends to lower electric field at the drain-channel junction and thus leads to improvement in the electrical performance of the transistor.
The implant species may be either p.sup.+ -type or n.sup.+ -type and the method thus is applicable to the manufacture of either PMOS or NMOS transistors - ie. it is applicable to CMOS processing. Channels of length less than or of the order 1.5 .mu.m can be exploited in transistors produced thus.
The invention thus improves operational reliability in small geometry transistors with no extra expense included during processing. A serious reliability hazard has thus been removed.
BRIEF INTRODUCTION OF THE DRAWINGS
In the drawings accompanying this specification:
FIGS. 1 to 3 show in illustrative cross-section steps in the application of the inventive method to the manufacture of an NMOS transistor; and,
FIG. 4 is an illustrative cross-section of a PMOS transistor, produced in a similar manner.
DESCRIPTION OF PREFERRED EMBODIMENTS
So that the invention may be better understood, embodiments will now be described, and reference will be made to the drawings. The description that follows is given by way of example only.
In the first step of the method, a gate oxide 1 and a polysilicon gate electrode 3 are formed on the surface of a silicon substrate 5. To this structure is added a layer of doped dielectric material--for example a sputtered oxide or spin-on glass containing phosphorus, arsenic or other suitable n-type dopant. This latter layer is then etched back by a reactive ion etch (RIE) or other anisotropic wet or dry etch technique to define small geometry sidewall structures 7.--See FIG. 1.
At the
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Tsang et al., "Fabrication of High-Performance LDD Fet's with Oxide Sidewall-Spacer Technology", IEEE Trans. On Ele. Dev., vol. ED-29, No. 4, Apr. 1982, pp. 590-596.
Foster David J.
Pickering Andrew J.
Hearn Brian E.
Plessey Overseas Limited
Thomas Tom
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