Method of making a high voltage planar edge termination structur

Details Method of making a high voltage planar edge termination structur Method of making a high voltage planar edge termination structur

1995-09-18

1998-02-03

Bowers, Jr., Charles L.

Fishing, trapping, and vermin destroying

437 40, 437 61, 437186, 437980, 148DIG45, 148DIG126, H01L 21765

Patent

active

057143960

ABSTRACT:
A semiconductor structure having an edge termination feature wherein a first doped region and a second doped region are selectively formed in a semiconductor layer. The second doped region is coupled with the first doped region and has an impurity concentration less than that of the first doped region. An insulating layer is disposed over the semiconductor layer and over at least a portion of the second doped region. A conductive layer, having a coil-shaped configuration, is disposed over the insulating layer and is coupled to the semiconductor layer.

REFERENCES:
patent: 4157563 (1979-06-01), Bosselaar
patent: 4947232 (1990-08-01), Ashida et al.
patent: 5086332 (1992-02-01), Nakagawa et al.
patent: 5105243 (1992-04-01), Nakagawa et al.
patent: 5113237 (1992-05-01), Stengl
patent: 5266831 (1993-11-01), Phipps et al.
patent: 5315139 (1994-05-01), Endo
patent: 5382825 (1995-01-01), Neilson
patent: 5382826 (1995-01-01), Mojaradi et al.
patent: 5498899 (1996-03-01), Palara
W. Feiler et al., IEEE TRans. Electron Dev. 39(6)(1992)1514 "Multistep field plates for HV planar p-n junctions", Jun. 1992.
D. Krizaj et al., 8th Int'l Symp. on Power Semic. Dev. & ICs (SPSD '96) p. 247, "Diffused spiral junction termination structure . . . ", May 1996.
Solid State Electronics, 1972, vol. 15, pp. 653-657, "Enhancement of Breakdown Properties of Overlay Annular Diodes by Field Shaping Resistive Films", L.E. Clark et al.
IEEE Electron Device Letters, vol. E1 L-6, No. 9, Sep. 1985, "A Proposed Planar Junction Structure with Near-Ideal Breakdown Characteristics", S. Ahmad et al.
Proceedings of the IEEE, vol. 55, No. 8, Aug. 1967, "High-Voltage Planar P-N Junctions", Y.C. Kao et al.
Proceedings of 1990 International Symposium on Power Semiconductors Devices and ICs, Tokyo, "Novel Planar Junction Termination Technique for High Voltage Power Devices", T. Stockmeier et al., pp. 236-239.
Proceedings of 1992 International Symposium on Power Semiconductor Devices & ICs, Tokyo, "High Voltage (4KV) Emitter Short Type Diode (ESD)", Mitsuhiko Kitagawa et al., pp. 60-65.

Affiliated with

Also associated with

Rating

Method of making a high voltage planar edge termination structur does not yet have a rating. At this time, there are no reviews or comments for this patent.

If you have personal experience with Method of making a high voltage planar edge termination structur, we encourage you to share that experience with our LandOfFree.com community. Your opinion is very important and Method of making a high voltage planar edge termination structur will most certainly appreciate the feedback.

Rate now

Comments { 0 }

Profile ID: LFUS-PAI-O-661802