Fishing – trapping – and vermin destroying
Patent
1993-02-04
1994-11-22
Fourson, George
Fishing, trapping, and vermin destroying
437 57, 437909, 437 56, 257369, 257500, H01L 21265
Patent
active
053669169
ABSTRACT:
A process for fabricating a high voltage CMOS transistor having a non-self aligned implanted channel which permits the operation of the device at high voltages. The non-self aligned implanted channel does not require alignment with the gate electrode of the CMOS device, but is accurately implanted early in the fabrication of the device through reliance on direct wafer stepper technology. As a result, the non-self aligned implanted channel does not require a high temperature drive, such that fabrication of the transistor is compatible with VLSI and ULSI processes, and the transistor can be up-integrated onto logic integrated circuits. Accuracy of the placement of the non-self aligned implanted channel provides for a shorter channel length, which enables the device to be highly area efficient while also increasing the current capability of the device. Furthermore, the transistor is characterized by a large field-induced avalanche breakdown voltage, enhanced by a thick gate oxide, a lightly doped drain, a field oxide region between the gate and the drain, and known field plating techniques.
REFERENCES:
patent: 4918026 (1990-04-01), Kosiak et al.
patent: 5014098 (1991-05-01), Schlais et al.
patent: 5047358 (1991-09-01), Kosiak et al.
patent: 5169794 (1992-12-01), Iranmaresh
Dolny et al., "Enhanced CMOS for Analog-Digital Power IC Applications," IEEE Trans. on Electron Devices, vol. ED-33, No. 12, pp. 1985-1991 (1986).
Editorial, "Technology to Watch-National's CMOS Process Tailored for Analog ICs" Electronics, Feb. 6, 1987, pp. 75-76.
Parrish Jack D.
Rusch Randy A.
Schnabel Douglas R.
Summe Richard A.
Booth Richard A.
Brooks Cary W.
Delco Electronics Corporation
Fourson George
Funke Jimmy L.
LandOfFree
Method of making a high voltage implanted channel device for VLS does not yet have a rating. At this time, there are no reviews or comments for this patent.
If you have personal experience with Method of making a high voltage implanted channel device for VLS, we encourage you to share that experience with our LandOfFree.com community. Your opinion is very important and Method of making a high voltage implanted channel device for VLS will most certainly appreciate the feedback.
Profile ID: LFUS-PAI-O-1991154