Method of making a high planarity, low CTE base for semiconducto

Details Method of making a high planarity, low CTE base for semiconducto Method of making a high planarity, low CTE base for semiconducto

1998-04-17

2000-04-04

Dutton, Brian

Semiconductor device manufacturing: process

Including control responsive to sensed condition

Electrical characteristic sensed

438 17, H01L 2100, H01L 2166, G01R 3126

Patent

active

060460601

ABSTRACT:
The present invention relates to a system and method for performing reliability screening on semi-conductor wafers and particularly to a highly planar burn in apparatus and method for uses including wafer level burn-in (WLBI), diced die burn-in (DDBI), and packaged die burn-in (PDBI). The burn-in system includes a burn-in substrate with a planar base, a temporary Z-axis connecting member, and a Z-axis wafer level contact sheet electrically coupled to one another for screening wafers, diced die, and packaged electronic components, their assembly and use.

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Pending U.S. Patent Application Serial No. 08/724,393, filed Oct. 1, 1996, entitled "A Reusable, Selectively Conductive, Z-Axis, Elastomeric Composite Substrate".

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