Method of making a high density floating gate electrically progr

Details Method of making a high density floating gate electrically progr Method of making a high density floating gate electrically progr

1977-01-26

1979-04-24

Ozaki, G.

Metal treatment

Process of modifying or maintaining internal physical...

Chemical-heat removing or burning of metal

148 15, 148188, 148189, 29569L, 29577R, 29577C, 357 45, H01L 21225, H01L 2126

Patent

active

041510216

ABSTRACT:
An N-channel, double level polysilicon, MOS read only memory or ROM array is electrically programmable by floating gates which are interposed between the gate oxide and control gates formed by polycrystalline silicon row address lines. The cells may be electrically programmed by applying selected voltages to the source, drain, control gate and substrate. A very dense array is obtained by a simplified manufacturing process which is generally compatible with standard N-channel silicon gate technology. Parallel strips of gate oxide, polycrystalline silicon, and nitride oxidation mask are applied, field oxide is grown, then a perpendicular pattern of strips is etched, removing field oxide as well as parts of the original strips, providing a diffusion mask. The second level polysilicon is then applied as strips overlying the original strips.

REFERENCES:
patent: 3893152 (1975-07-01), Line
patent: 3914855 (1975-10-01), Cheney et al.
patent: 3927468 (1975-12-01), Anthony et al.
patent: 3958323 (1976-05-01), De La Moneda
patent: 4055444 (1977-10-01), Rao
patent: 4075045 (1978-02-01), Rideout

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