Method of making a high-density DRAM structure on SOI

Details Method of making a high-density DRAM structure on SOI Method of making a high-density DRAM structure on SOI

1994-11-22

1995-11-14

Thomas, Tom

Fishing, trapping, and vermin destroying

437 21, 437 60, 437203, 437919, H01L 218242

Patent

active

054666252

ABSTRACT:
A high density, DRAM cell array with a very short channel, vertical gate transfer transistor that can be manufactured using conventional photolithography process steps. The conventional four-by-four DRAM array shown schematically in FIG. 1a is rearranged to the shared-gate, double-bit array shown schematically in FIG. 1b. Trench storage capacitors and vertical FET transistors are arranged in pairs with a common vertical gate and a common substrate, allowing both bit and substrate contacts to be shared by adjacent cells.

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