Method of making a heterojunction bipolar transistor with SIPOS

Details Method of making a heterojunction bipolar transistor with SIPOS Method of making a heterojunction bipolar transistor with SIPOS

1986-05-19

1988-01-05

Hearn, Brian E.

Fishing, trapping, and vermin destroying

437 68, 437106, 437126, 437196, 437203, 357 34, 427 51, 156614, H01L 21265, H01L 2972

Patent

active

047176814

ABSTRACT:
A wafer process flow encompasses an arbitray repeated layered structure of heteroepitaxial layers of silicon based films with process control throughout the strata of chemical potential and recombination velocity, suitable for both high performance MOS and bipolar transistors with three dimensional transistor capability. A non-compensated doping technique preserves crystalline periodicity, as does the component delineation by means of anisotropic etching. The wafer is hermetic by means of the semi-insulation films polyimide, and the elimination of phosphorous doped silicon dioxide. A metallurgy system enables a high level integration.

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