Method of making a GaAs JFET with self-aligned p-type gate by ou

Details Method of making a GaAs JFET with self-aligned p-type gate by ou Method of making a GaAs JFET with self-aligned p-type gate by ou

1990-02-08

1991-05-14

Hearn, Brian E.

Fishing, trapping, and vermin destroying

437160, 437911, 148DIG88, 148DIG82, H01L 2124

Patent

active

050155962

ABSTRACT:
A GaAs JFET according to the present invention is formed as follows. First, an n type active layer is formed on a GaAs substrate. Then, a gate electrode containing a group II element is formed on the n type active layer. With the gate electrode being used as a mask, an n type impurity is ion-implanted in the GaAs substrate with a high concentration in a self-aligned fashion with respect to the gate electrode. Heat-treatment is then performed on the resultant structure to diffuse the group II element in the gate electrode into the n type active layer, forming a p type gate region. At the same time, the ion-implanted n type impurity is activated, forming source and drain regions.

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