Method of making a flash memory cell having an asymmetric source

Fishing – trapping – and vermin destroying

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437 43, H01L 218247, H01L 21265

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active

057834571

ABSTRACT:
A method of making a flash memory cell includes patterning a series of layers over a semiconductor substrate of a first conductivity type to form a gate electrode structure. A first ion implantation procedure is performed to introduce a first impurity of a second conductivity type into the semiconductor substrate and form a heavily-doped source region and a heavily-doped drain region. A second ion implantation procedure is performed at a tilt angle of 25.degree. to 45.degree., to introduce a second impurity of the second conductivity type into the semiconductor substrate and form a pair of asymmetric lightly-doped regions, with one of the asymmetric lightly-doped regions surrounding the heavily-doped source region, and the other of the asymmetric lightly-doped regions beneath the heavily-doped drain region. An insulating spacer is formed on sidewalls of the gate electrode structure. A photoresist layer is coated over exposed surfaces of the gate electrode structure, the insulating spacer, and the heavily-doped source region and drain region. The photoresist layer is patterned to form an opening and expose a portion of the gate electrode structure, the insulating spacer, and the heavily-doped drain region. The exposed portion of the insulating spacer is removed. A third ion implantation procedure is performed at a tilt angle of 25.degree. to 45.degree., to introduce an impurity of the first conductivity type into the semiconductor substrate and form a heavily-doped pocket region surrounding the heavily-doped drain region. The photoresist layer is then removed.

REFERENCES:
patent: 5316961 (1994-05-01), Okazawa
patent: 5366915 (1994-11-01), Kodama
patent: 5432106 (1995-07-01), Hong
patent: 5510279 (1996-04-01), Chien et al.
patent: 5518942 (1996-05-01), Shrivastava
patent: 5595919 (1997-01-01), Pan

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