Method of making a field effect transistor with submicron channe

Details Method of making a field effect transistor with submicron channe Method of making a field effect transistor with submicron channe

1994-03-22

1995-06-20

Hearn, Brian E.

Fishing, trapping, and vermin destroying

437 27, 437 30, H01L 21265

Patent

active

054260639

ABSTRACT:
A method for manufacturing a semiconductor device including steps of forming a gate oxide film and a gate electrode on a semiconductor substrate; implanting impurity ions of the same conductivity as the substrate in an oblique direction at a first tilt angle to the normal line of the substrate and with a first acceleration voltage and dose, while rotating the substrate about the normal line thereof; implanting impurities of the same conductivity as the substrate in the same manner except for using a tilt angle to the normal line which is greater and a dose is smaller than that of the first tilt angle and dose; and forming source and drain regions by implanting impurity ions of the opposite conductivity to the substrate into the substrate, followed by performing a thermal treatment.

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patent: 6218221 (1993-06-01), Okumura
Wolf et al., vol. I, Silicon Processing for the VLSI Era, Lattice Press, 1986, pp. 292-294.
Okumura et al., "Mechanism Analysis of a Highly Reliable Graded Junction Gate/N.sup.- Overlapped Structure in MOS LDD Transistor", Extended Abstracts of 21st Conference on Solid State Devices & Materials, Tokyo 1989, pp. 477-480, LSI R & D Laboratory, Mitsubishi Corp.

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