Stock material or miscellaneous articles – All metal or with adjacent metals – Composite; i.e. – plural – adjacent – spatially distinct metal...
Reexamination Certificate
2000-11-27
2003-09-16
Thomas, Tom (Department: 2811)
Stock material or miscellaneous articles
All metal or with adjacent metals
Composite; i.e., plural, adjacent, spatially distinct metal...
C438S622000, C438S618000
Reexamination Certificate
active
06620526
ABSTRACT:
FIELD OF THE INVENTION
The present invention relates to a method of fabricating integrated circuits, and specifically, to a method of the manufacture a dual damascene structure that may reduce the possibility of misalignment.
BACKGROUND OF THE INVENTION
The large integration of semiconductor ICs has been accomplished by a reduction in individual device size. As the integration level of semiconductor devices increases, each cell generally is reduced in size. To provide for such reduction in cell size, various techniques have been used to improve the performance of the device. For example, the cell capacitance of DRAM has been increased by increasing the effective area of a cell capacitor. To increase the capacitor's effective area, stacked-capacitor and trench-capacitor structures, as well as combinations thereof, have been developed. With this reduction of device size, many challenges arise in the manufacture of the ICs. Each device requires interconnections for exchanging electrical signals from one device to another device. Specially, the high performance integrated circuits have multi-level connections. Additional miniaturization is highly desirable for improved IC performance and cost reduction. Interconnects provide the electrical connections between the various electronic elements of an IC and they form the connections between these elements.
Many devices, such as DRAMs, include conductive lines for performing certain function and bit line contacts, storage node contacts formed in DRAM's unit cell. Thus, design rules for minimizing area and ensuring adequate process margin are required. A variety of techniques are employed to create interconnect lines and vias. One such technique involves a process generally referred to as dual damascene, which includes forming a trench and an underlying via hole. The trench and the via hole are simultaneous filled with a conductor material, thereby simultaneously forming an interconnect and an underlying plug. This is a preferred structure for low RC interconnect structures. Interconnect structures containing copper are typically fabricated by a Damascene process.
The prior art that relates to the field of the Dual Damascene process is disclosed in U.S. Pat. No. 6,140,226 to Grill, et al., entitled “Dual damascene processing for semiconductor chip interconnects.” A further prior art may refer to U.S. Pat. No. 6,133,140 to Yu, et al., entitled “Method of manufacturing dual damascene utilizing anisotropic and isotropic properties”.
One of the patents related to the dual damascene is disclosed in U.S. Pat. No. 6,077,770. First, as show in
FIG. 1
, a substrate structure
200
having a dielectric layer
202
formed thereon. Trenches
204
a
,
204
b
and
204
c
are formed in the dielectric layer
202
. Next, as shown in
FIG. 2
, a layer of conductive material
206
a
′,
206
b
′,
206
c
′ is deposited over the substrate
200
and is filled into the trenches
204
a
,
204
b
and
204
c
. Next, a portion of the conductive lines within the dielectric layer
202
is removed.
Next, as shown in
FIG. 3
, an insulation layer is formed over the dielectric layer
202
. For example, the insulation layer can be a silicon nitride layer formed using, for example, a chemical vapor deposition method. Thereafter, a chemical-mechanical polishing (CMP) method is used to planarize the insulation layer until the dielectric layer
202
is exposed. Ultimately, cap layers
208
a
,
208
b
and
208
c
are formed within the respective trenches
204
a
,
204
b
and
204
c
above the conductive lines
206
a
′,
206
b
′ and
206
c
′. Another dielectric layer
212
a
is formed over the dielectric layer
202
and the cap layers
208
a
,
208
b
′ and
208
c
, as shown in
FIG. 3
, an opening
214
in the dielectric layer
212
a
. Some time the misalignment situation will occurred, the opening
214
exposes the cap layer
208
b
. As shown in
FIG. 3
, only the side walls of the cap layer
208
b
and the conductive line
206
b
′ are exposed.
Next, as shown in
FIG. 4
, the cap layer
208
b
above the conductive line
206
b
′ is removed using a wet etching method. A cavity
216
is formed underneath the dielectric layer
212
a
. Next, as shown in
FIG. 5
, a glue/barrier layer
218
conformal to the surface of the opening
214
and the cavity
216
is deposited over the substrate
200
. The glue/barrier layer
218
can be made from conductive material including titanium/titanium nitride (Ti/TiN) or tantalum/tantalum nitride (Ta/TaN). Thereafter, a conductive layer
220
is deposited over the substrate
200
by a chemical vapor deposition. Subsequently, an etching back or a chemical-mechanical polishing operation is carried out to remove excess conductive material above the dielectric layer
212
a.
However, the method mentioned about has to laterally etch the nitride cap, and then laterally forming a material refilled into the trench
216
. If the deposition condition is not good enough, it will result the conductive line opening that causes the yield drop or the resistance increases.
What is needed is a method of connecting the line under the misalignment for dual damascene.
SUMMARY OF THE INVENTION
The object of the present invention is to form a conductive plug when misalignment occurred for dual damascene.
A method for manufacturing a dual damascene structure comprises patterning a first isolation layer over a substrate. A trench is formed into the first isolation layer. A sacrificial layer is formed along a surface of the etched substrate. A conductive layer is formed on the dielectric layer. A portion of the conductive layer is removed, thereby forming a conductive structure in the trench.
A second isolation layer is formed on the first isolation layer and the conductive layer. An opening in the second isolation layer and the first isolation layer is formed, wherein the opening at least exposes a portion of the sacrificial layer attached on side wall of the conductive structure. The sacrificial layer attached on the side wall of the conductive structure is removed via the opening, thereby forming a cavity adjacent to the conductive structure. Then, a conductive material is refilled in the cavity and the opening to connect to the conductive structure.
REFERENCES:
patent: 5466636 (1995-11-01), Cronin et al.
patent: 5883434 (1999-03-01), Noguchi
patent: 6348733 (2002-02-01), Lin
Cheng Clement
Owens Douglas W.
Thomas Tom
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