Semiconductor device manufacturing: process – Making device array and selectively interconnecting – Using structure alterable to conductive state
Reexamination Certificate
2000-04-27
2001-06-26
Niebling, John F. (Department: 2812)
Semiconductor device manufacturing: process
Making device array and selectively interconnecting
Using structure alterable to conductive state
C438S600000
Reexamination Certificate
active
06251710
ABSTRACT:
FIELD OF THE INVENTION
The present invention relates to interconnect structures, and more particularly to interconnect structures such as anti-fuse structures in which an anti-fuse dielectric material is formed in the structure prior to formation of the vias and wires.
BACKGROUND OF THE INVENTION
The manufacture of integrated circuits (ICs) typically includes the formation of metallization layers which are patterned to provide interconnection between devices. Some IC interconnections are programable, either with fuses or anti-fuses. Unprogrammed fuses provide a low resistance link between or within metallization layers which can be programmed by being blown. That is, the fuse can be caused to be non-conductive by applying a sufficiently high current across it to blow.
Anti-fuses operate in the opposite fashion, i.e., the unprogrammed structure used to form the anti-fuse has an intrinsically high resistance, and the programmed structure has a relatively low resistance. By applying a programmable current, the electrical resistance through the anti-fuse material is greatly reduced providing a conductive link between or within metallization levels. Typical prior art anti-fuse materials include: amorphous silicon, amorphous carbon, carbon, germanium, selenium, compound semiconductors such as GaAs, SiC, AlP, InSb and CdTe, and ceramics such as Al
2
O
3
.
One prior art anti-fuse structure is shown in FIG.
1
. Specifically, the structure shown in
FIG. 1
comprises a substrate
12
such as a Si wafer. An oxide layer
14
overlays the substrate, and can be formed by a variety of well known deposition processes such as chemical vapor deposition. A metal layer
16
is then formed on the oxide layer utilizing conventional deposition processes such as evaporation or sputtering. A second oxide layer
18
is formed over the metal layer and a via
20
is formed in the second oxide layer utilizing conventional lithography and reactive-ion etching (RIE). One of the above mentioned anti-fuse materials is then formed in the via to form an anti-fuse structure
22
. A second metal layer
24
is then formed over the structure.
Programming of the anti-fuse structure of
FIG. 1
can be accomplished by providing a voltage of 4-10 volts between the metal layers. Before programming, the anti-fuse structure typically has a resistance of above 1 giga-ohm for a 1 &mgr;m diameter via. A programmed anti-fuse forms a conductive path
26
between the metal layers having a resistance of about 20-100 ohms.
Anti-fuse structures allow for much higher programable interconnection densities than standard fuse structures as well as smaller current and power for the non-programmed elements. A major problem with prior art anti-fuse structures is that dedicated lithographic masking levels are required to fabricate the same. Not only does the use of such dedicated lithographic masking levels add additional cost to the overall process, but it adds to the complexity of the same.
In view of the above mentioned problems with prior art anti-fuse structures, there is a continued need to develop a new and improved method in which an anti-fuse structure is fabricated without employing dedicated lithographic masking levels.
Co-assigned U.S. application Ser. No. 09/469,374, filed Dec. 22, 1999, describes one method of forming an interconnect structure wherein dedicated masking levels are not employed. In the '374 application, an interlevel dielectric (ILD) layer is formed on top of a substrate having a first level of electrically conductive features formed therein and then vias, at least one via being a slot via, are formed in the ILD layer to expose portions of the first level of electrically conductive features. Next, a conformal anti-fuse material is formed on the ILD and the anti-fuse material is patterned to form spaces in which a second level of electrically conductive features is formed. Etching is conducted to remove anti-fuse material from the spaces and the vacant spaces are then filled with a conductive material.
Alternative methods to the one disclosed in the '374 application are continuously being sought in which fewer processing steps are employed. The present invention describes an alternative method to the method disclosed in the '374 application and it represents an improvement since the anti-fuse material is formed on the surface of the substrate prior to ILD deposition. This eliminates extra processing steps required in the '374 application to create a standard contact; therefore the impact and/or influence on the contact itself is greatly minimized.
SUMMARY OF THE INVENTION
One object of the present invention is to provide a method of fabricating an interconnect structure in which an anti-fuse material is formed in the structure without the need of employing dedicated lithographic masking levels.
Another object of the present invention is to provide a method in which the anti-fuse material is formed on the surface of a substrate prior to forming vias in an interlevel dielectric layer of an interconnect structure.
A still further object of the present invention is to provide a method in which an anti-reflective coating is employed as the anti-fuse material.
A yet further object of the present invention is to provide a method which is simpler than existing prior art methods, yet is capable of creating a standard contact in which the impact on the contact has been significantly minimized.
These and other objects and advantages are achieved in the present invention by employing the following method which includes the steps of:
(a) forming an anti-fuse dielectric layer on a surface of a substrate, said substrate having a first level of electrically conductive features;
(b) forming an interlevel dielectric layer on said anti-fuse dielectric layer;
(c) forming vias in said interlevel dielectric layer exposing portions of said anti-fuse dielectric layer that overlay said first level of electrically conductive features;
(d) forming a wire level mask on said interlevel dielectric layer, wherein at least of one of said vias and a portion of said interlevel dielectric layer are left exposed;
(e) etching exposed portions of said anti-fuse dielectric layer from said exposed vias, wherein during said etching a portion of said exposed interlevel dielectric layer is removed so as to form a space wherein a second level of electrically conductive features will be subsequently formed;
(f) stripping said wire level mask; and
(g) filling said vias including said spaces with a conductive material, whereby said second level of electrically conductive features is formed.
An optional planarization step may follow filling step (g). Moreover, a multilevel interconnect structure may be formed from the structure provided in steps (a)-(g) by utilizing conventional processing steps that are well known in the art. Additionally, in one embodiment of the present invention, process steps (a)-(g) are repeated any number of times to provide an interconnect structure in which each successive interconnect level includes a patterned anti-fuse dielectric layer formed thereon.
In another embodiment of the present invention, metal reactive-ion etching is employed in fabricating a multilevel interconnect structure in which the uppermost wiring level contains patterned conductive regions wherein the contact to the lower metal region is through a tapered contact.
The vias formed in the present invention may be slot vias which consists of an enlarged contact via that provides increased in overlay tolerance with the next contact via; stacked vias in which the contact is formed slightly skewed from the previous via or wire level; standard vias in which the contact is formed over the previous via or wiring level; or any combinations thereof.
The present invention also provides interconnect structures in which a patterned anti-fuse material containing an opening to a first level of electrically features is formed on the surface of a substrate. Specifically, the interconnect structure of the present invention comprises:
a substrate having a fi
Brintzinger Axel C.
Radens Carl J.
Capella Steven
Gurley Lynne A.
International Business Machines - Corporation
Niebling John F.
Scully, Scott, Murphy and Presser
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