Method of making a double layered floating gate EPROM with trenc

Details Method of making a double layered floating gate EPROM with trenc Method of making a double layered floating gate EPROM with trenc

1994-11-17

1996-09-24

Fourson, George

Fishing, trapping, and vermin destroying

437 67, 437984, 437191, 257316, H01L 218247

Patent

active

055590489

ABSTRACT:
The present invention provides a novel double-layered floating gate memory transistor wherein drain and source regions are self-aligned with respect to a first floating gate layer and isolations regions that isolate the memory cell regions on which the memory transistors are formed are also self-aligned but with respect to a second floating gate layer overlying the first floating gate layer.

REFERENCES:
patent: 5173436 (1992-12-01), Gill et al.
patent: 5208179 (1993-05-01), Okazawa
patent: 5229316 (1993-07-01), Lee et al.
patent: 5352619 (1994-10-01), Hong
patent: 5413946 (1995-05-01), Hong

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