Semiconductor device manufacturing: process – Making device array and selectively interconnecting – Using structure alterable to conductive state
Patent
1997-06-20
1999-07-13
Niebling, John F.
Semiconductor device manufacturing: process
Making device array and selectively interconnecting
Using structure alterable to conductive state
438600, 438661, 438662, 438598, H01L 2182
Patent
active
059239603
ABSTRACT:
An integrated circuit includes a substrate with doped regions, a patterned polysilicon layer defining contacts and local interconnects, a submetal dielectric, a two-metal layer metal interconnect structure with an intermetal dielectric layer, and a passivation layer. Like the dielectric layers, the passivation layer is optically transparent, thick, and planarized. Because of this, laser energy can be directed through the passivation layer to fuse two conductors of the top metal layer without delaminating the passivation layer. In addition, laser energy is directed through the passivation layer and the intermetal dielectric to fuse pairs of conductors in the lower metal layer. Thus, the present invention provides for reliable convenient circuit modification without disturbing dielectric and exposing metal features to moisture and other contaminants.
REFERENCES:
patent: 4681778 (1987-07-01), Young
patent: 5087589 (1992-02-01), Chapman et al.
patent: 5793095 (1998-08-01), Harvey
Anderson Clifton L.
Gurley Lynne A.
Niebling John F.
VLSI Technology Inc.
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