Method of making a complementary BiCMOS process with isolated ve

Details Method of making a complementary BiCMOS process with isolated ve Method of making a complementary BiCMOS process with isolated ve

1990-07-20

1991-04-30

Hearn, Brian E.

Fishing, trapping, and vermin destroying

437 56, 437 31, 437 57, 437 59, 437 54, 357 44, 357 43, 148DIG9, H01L 21265

Patent

active

050117840

ABSTRACT:
A BiCMOS process which provides both isolated and vertical NPN and PNP transistors with better performance characteristics and fewer additional steps than the prior art. The additional steps consist of masked implants with no changes in the thermal steps of the CMOS process. An N-well to contain the vertical PNP transistor is formed during the same step that the NPN vertical transistor collector is formed. The N base of the PNP transistor is formed by implanting an N type material. A P type material is implanted at a high energy of at least 300 keV (150 for doubly ionized Boron) to form a collector of the PNP transistor. A P region is then formed as an emitter of PNP transistor. The high energy P implant gives a peak at approximately 0.8 .mu.m below the surface to form the equivalent of a buried layer (without growing an epitaxial layer after a P implant to form a buried layer as in the prior art). The advantages of a sharp profile of the high energy P implant are maintained by performing this step near the end of the process to prevent the profile from being flattened by subsequent thermal steps. A flat base structure improves the devices' performance and is preferably provided by doing the N base implantation early in the process and allowing the temperature of later steps to drive the implanted ions deeper to provide a flat profile.

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Wolf, Stanley, Silicon Processing for the VLSI Era, vol. 2: Process Integration Lottice Press, Sunset Beach, CA (1990), pp. 523-553.

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