Method of making a capacitor for an integrated circuit

Details Method of making a capacitor for an integrated circuit Method of making a capacitor for an integrated circuit

1993-09-23

1994-07-19

Thomas, Tom

Fishing, trapping, and vermin destroying

437 47, 437 52, 437919, H01L 2170

Patent

active

053309316

ABSTRACT:
A method is provided for forming a capacitor structure for a memory element of an integrated circuit. The method comprises providing a first conductive electrode, forming a layer of a first dielectric material thereon, opening a via hole through the dielectric layer, providing within the via opening a capacitor dielectric having a higher dielectric strength than the first dielectric, the capacitor dielectric contacting the first electrode, planarizing the resulting structure and then forming a second conductive electrode thereon. Preferably, when the second dielectric comprises a ferroelectric dielectric material, sidewalls of the via opening are lined with a dielectric barrier layer to provide diffusion barrier between the ferroelectric and first dielectric layer. Advantageously, planarization is accomplished by chemical mechanical polishing to provide fully planar topography. The method provides a capacitor of a simple, compact structure which may be integrated with CMOS, Bipolar and Bipolar CMOS processes for submicron VLSI and ULSI integrated circuits.

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Process Technology Developments for GaAs Ferroelectric Nonvolatile Memory, L. E. Sanchez, I. K. Naik; S. H. Watanabe; I. E. Leybovich; J. H. Madok and S. Y. Wu.

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