Method of making a buried bit line DRAM cell

Details Method of making a buried bit line DRAM cell Method of making a buried bit line DRAM cell

1994-02-07

1994-11-15

Hearn, Brian E.

Fishing, trapping, and vermin destroying

437919, 437985, H01L 21266

Patent

active

053648080

ABSTRACT:
Ions of dopant are implanted into predetermined locations in a doped semiconductor substrate in sufficient concentration to form a buried conductor regions. A thick dielectric layer overlies the surface of the doped substrate. A first polysilicon layer is formed and patterned on the silicon dioxide layer by a mask and etching to form conductor lines, covered by a dielectric. A second polysilicon layer is formed on the second dielectric layer and patterned to form a first capacitor plate. A third dielectric layer is formed on the surface of the second polysilicon layer. A third polysilicon layer is formed on the third dielectric layer and patterned to form a top capacitor plate. A layer of BPSG is deposited upon the third layer of polysilicon.

REFERENCES:
patent: 4958318 (1990-09-01), Harari
patent: 4959698 (1990-09-01), Shinichi
patent: 4970564 (1990-11-01), Kimura et al.
patent: 5188975 (1993-02-01), Kojima et al.
patent: 5286668 (1994-02-01), Chou
patent: 5296400 (1994-03-01), Park et al.

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