Semiconductor device manufacturing: process – Forming bipolar transistor by formation or alteration of... – Sidewall base contact
Reexamination Certificate
2002-01-28
2004-10-26
Lee, Eddie (Department: 2811)
Semiconductor device manufacturing: process
Forming bipolar transistor by formation or alteration of...
Sidewall base contact
C438S350000, C438S375000, C438S367000, C438S564000, C257S554000, C257S588000, C257S552000
Reexamination Certificate
active
06808999
ABSTRACT:
BACKGROUND OF THE INVENTION
1. Field of the Invention
The present invention relates to a bipolar transistor and a method of fabricating the same.
2. Description of Related Art
Recently, in the field of semiconductor devices such as LSIs, there have been strong demands toward enhancement in performance of bipolar transistors. The enhancement in the performance of bipolar transistors can be achieved by the shortening of a base transit time due to shortening of a base thickness by lowering of a base resistance, and by reduction of a parasitic capacitance represented by a base-collector capacitance.
FIGS. 4A
to
4
C and
FIGS. 5A
to
5
C are process diagrams illustrating a method of fabricating a high speed bipolar transistor (npn-type).
The bipolar transistor shown in these figures is of a double polysilicon structure in which an emitter electrode and a base electrode are formed of a poly-Si film
8
and a p-type poly-Si film
3
, respectively. In this structure, the emitter electrode is isolated from the base electrode by means of an insulating side wall
7
a
for significantly reducing a base-collector capacitance. Moreover, the base transit time is shortened by making shallower the diffusion depth of the base for reducing a base thickness using a low energy ion implantation technique.
The bipolar transistor having the above-described structure is fabricated in the following procedures. First, as shown in
FIG. 4A
, an insulating film (SiO
2
film)
2
having a thickness of from 100 to 200 nm is formed over the surface of a silicon substrate
1
by or CVD.
As shown in
FIG. 4B
, an opening is formed for a base electrode of the bipolar transistor. Reference numeral
2
a
indicates an opening side wall. A p-type polysilicon (poly-Si) film
3
having a thickness of from 100 to 200 mm is formed over the surface by CVD. The p-type poly-Si film
3
serves as a base electrode. It is to be noted that the doping of a p-type impurity to the poly-Si can be also performed by ion implantation.
Next, as shown in
FIG. 4C
, an insulating film (SiO
2
film)
4
having a thickness of from 300 to 400 nm is formed over the surface of the wafer by CVD, and then an opening
10
for forming an emitter and a base is formed by dry etching, of the laminated films, the SiO
2
film
4
and the p-type poly-Si film
3
. After that, an insulating film (SiO
2
film)
5
having a thickness of from 10 to 20 nm is formed over the surface by CVD, and a p-type impurity diffusion layer
6
is formed by ion implantation through the SiO
2
film
5
. In this case, for example, ions of BF
2
are implanted in a dose of from 1×10
13
to 1×10
14
cm
−2
at an implantation energy of from 20 to 30 KeV. The p-type impurity diffusion layer
6
serves as the base, and the SiO
2
film
5
having a thickness of from 10 to 20 nm serves as a buffer layer for preventing a channeling tail upon ion implantation for forming the base. The ion implantation is followed by heat-treatment (annealing) for 10 to 20 minutes at 900° C., to form a P
+
contact layer (graft contact)
3
a
in the silicon substrate
1
by diffusion from the p-type poly-Si film
3
.
Next, as shown in
FIG. 5A
, a side wall forming insulating film (SiO
2
film)
7
having a thickness of from 400 to 600 nm is formed over the surface by CVD. The SiO
2
film
7
is then removed by anisotropic etching such as RIE so as to form side walls
7
a
made of the SiO
2
film in the opening for forming an emitter and abase, as shown in FIG.
5
B. The side wall
7
a
has a function of isolating the base electrode made of the p-type poly-Si film
3
from an emitter electrode which will be formed later.
As shown in
FIG. 5C
, a poly-Si film
8
having a thickness of from 100 to 200 nm is patterned over the surface by CVD. The poly-Si film
8
thus patterned serves as the emitter electrode. The poly-Si film
8
is implanted with (n
+
) ions, followed by heat-treatment, thus forming an emitter
9
as the n-type impurity diffusion layer. In this case, for example, ions of As are implanted in a dose of from 5×10
15
to 2×10
16
cm
−2
at an implantation energy of from 30 to 70 KeV. The ion implantation is followed by heat-treatment (annealing) for 10 to 20 minutes at 900° C. for performing diffusion of the emitter and base.
After that, while being not shown in the figure, each wiring for the base electrode, emitter electrode and the like is performed using a general wiring technique.
In the bipolar transistor having the above-described base-emitter structure, the concentration of the base
6
at a portion directly under the emitter
9
is high, and thereby an emitter-base withstand voltage is determined at this portion, thus obtaining only a withstand voltage from 2 to 4 V.
To apply such a bipolar transistor to TTLI/0 or the like, an emitter-base withstand voltage of about 3.5 V or more is required. Therefore, in general, the emitter-base withstand voltage is required to be ensured by increasing an ion implantation energy upon formation of the base
6
(see
FIG. 4C
) for reducing an impurity concentration of the base at the emitter-base unction.
However, such a method of enhancing the withstand voltage has the following disadvantages:
(1) The concentration of the base
6
is reduced at a portion directly under the side wall
7
a
for isolating the emitter
9
from the base
6
, and consequently, at such a portion, a collector current or base re-recombination current tends to be varied, thus increasing variations in characteristics and reducing reliability.
(2) The thickness of the base
6
is extended by applying the high energy ion implantation to the base
6
, with a result that the base transit time is increased, thus reducing the operating speed.
SUMMARY OF THE INVENTION
An object of the present invention is to provide a bipolar transistor with high performance and high reliability, which is obtained by enhancing an emitter-base withstand voltage.
To achieve the above object, according to a first aspect of the present invention, there is provided a bipolar transistor comprising:
A bipolar transistor comprising:
A semiconducting substrate; a first impurity diffusion layer having a first conducting type, which is formed in the semiconducting substrate;
a first conductive film connected to the first impurity diffusion layer;
an opening portion formed in the first conductive layer;
a second impurity diffusion layer having the first conducting type, which is formed at least in a portion, exposed from the opening portion, of the semiconducting substrate in such a manner as to be connected to the first impurity diffusion layer;
a third impurity diffusion layer having the first conducting type, which is formed in the semiconducting substrate in such a manner as to contain the second impurity diffusion layer, the second impurity diffusion layer having a surface impurity concentration equal to or more than that of the third impurity diffusion layer;
side walls formed of an insulating film in the opening portion; and
a fourth impurity diffusion layer having a second conducting type, which is formed at least in a portion, exposed from the opening portion surrounded by the side walls, of the semiconducting substrate and in the third impurity diffusion layer, the second impurity diffusion layer having a diffusion depth equal to or less than that of the fourth impurity diffusion layer.
In the above bipolar transistor, preferably, the first impurity diffusion layer is a base contact; the third impurity diffusion layer is a base; the second impurity diffusion layer is a connecting layer between the base contact and the base; and the fourth impurity diffusion layer is an emitter.
According to a second aspect of the present invention, there is provided a bipolar transistor comprising:
a semiconducting substrate:
a first impurity diffusion layer having a first conducting type, which is formed in the semiconducting substrate;
a first conductive film connected to the first impurity diffusion layer;
an opening portion formed in the first conductive layer
Gebremariam Samuel A
Kananen Ronald P.
Lee Eddie
Rader & Fishman & Grauer, PLLC
Sony Corporation
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