Multiplex communications – Communication over free space – Combining or distributing information via time channels
Reexamination Certificate
1998-12-21
2003-01-21
Kizou, Hassan (Department: 2662)
Multiplex communications
Communication over free space
Combining or distributing information via time channels
C370S350000, C370S395100, C370S503000
Reexamination Certificate
active
06510150
ABSTRACT:
BACKGROUND OF THE INVENTION
The present invention relates generally to systems and methods that enable multiple-access of the same channel in a network, and, more particularly, to a system and method of timestamp synchronization in a network that employs a reservation-based TDMA protocol.
In general, communications networks, particularly wireless networks, typically employ a multiple-access protocol that is designed to prevent collisions of data packets due to simultaneous transmission of the data packets by multiple transmitters in the network using the same channel. One protocol that has come into widespread use is known as Time-Division Multiple Access (TDMA). A detailed description of this technique can be found in the reference book
Telecommunications Networks: Protocols, Modeling and Analysis,
Addison-Wesley, 1997. In general, in accordance with the TDMA protocol, channel time is divided into small time slots, each of which is assigned to a different node (user). This time slot assignment can either be fixed (classical TDMA), or variable (reservation-based TDMA). In either case, since the number of nodes (users) is finite the data is usually transmitted in TDMA “frames”, which ensure that the delays encountered by the different users are finite.
For example, in fixed-assignment TDMA, the TDMA frame consists of the total number of slots assigned to all users, after which the TDMA frame repeats. In the case of reservation-based TDMA, a natural framing occurs in terms of different “phases” of the TDMA frame, consisting typically of a “control” phase in which reservations are requested and assigned, and a “data” phase in which the data is transmitted by the different users in their respective assigned time slots.
It is necessary that all transmitters and receivers in the TDMA network be synchronized in terms of the TDMA frame. An incorrectly synchronized transceiver, at best, cannot communicate, but, at worst, can cause the entire TDMA network to collapse if appropriate safeguards are not built into the protocol. It should be recognized that TDMA frame synchronization is not the same as clock synchronization of a modem, which is a function of the Physical layer (PHY). Usually, frame synchronization is achieved using a centralized control strategy implemented by a central controller (CC). However, frame synchronization can also be implemented in a distributed fashion.
In most TDMA networks, a universal time reference is required to properly allocate resources for transmission. This universal time reference is usually provided in the form of a “timestamp”, e.g., which specifies the current time. The timestamps are broadcast periodically by the central controller, and are used by the end terminals (WTs) to synchronize their “timestamp” registers.
For variable-sized TDMA frames, synchronization achieved through the use of timestamps typically requires the utilization of a phase-locked loop (PLL) in each of the WTs, which can be quite complex. Further, the PLLs used for this purpose must be redesigned whenever the parameters of the timestamp scheme are changed, for example, when the frequency of timestamp transmission is changed. In this connection, a generic synchronization scheme is desired in order to enable an WT to be used interchangeably within many different networks.
Most protocols have an interval during which the timestamp update must be sent. Otherwise, the timing jitter may be larger than what can be handled by a particular application, e.g., an MPEG decoder. For a reservation-based TDMA protocol, there are many problems with the timestamp-based approach. The first problem is that the transmission of the timestamp value must also be reserved, and subsequently, other data must also be queued for transmission. In order to ensure efficient use of processor resources (which must be used for managing many other functions), this queuing is usually scheduled in advance. However, the timestamp value cannot be obtained until the exact time of transmission. Further, the queuing of the data packets behind the timestamp value cannot be done before the timestamp value is obtained. Of course, it is possible to switch the data stream between two separate queues with one holding the timestamp value and the other holding the data. However, this solution is quite complicated and requires precise synchronization.
A more detailed understanding of this problem can be gained by considering the case of a wireless asynchronous transfer mode (ATM) network that uses a reservation-based medium-access control (MAC) protocol. The MAC protocol implementation depends on a periodic control-data-frame (CDF), as described in pending U.S. patent application Ser. No. 08/770,024 filed on Dec. 19, 1996, now U.S. Pat. No. 6,198,728, and incorporated by reference herein. Each CDF contains many phases, during which both control and data information is sent from both the base station (BS) and the wireless terminal (WT). In the context of the implementation shown in the drawings and discussed hereinafter, the BS corresponds to the previously described central controller (CC) and the WT corresponds to the previously described end terminal (WT).
FIG. 1
illustrates the four phase structure, namely, BS_SIG; DN_DATA; UP_DATA; and, E_BURST. A brief description of each of these phases follows:
BS_SIG: During this phase, the BS sends control information for the downlink. The timestamp packet is normally sent during this phase. At the BS, the processor starts the transmission of packets from BS. At the WT, the WT starts the process of reception of packets from the BS.
DN_DATA: During this phase, the BS sends data packets for the WTs. At the BS, the processor is busy interpreting the packets sent by the WT during the UP_DATA phase. At the WT, the processor is busy storing the PHY FIFO for the next burst of transmission during the UP_DATA phase.
UP_DATA: During this phase, the WT sends data and signaling packets for the BS. Signaling is sent using superslots. At the BS, the processor is busy storing the PHY FIFO for the next burst of transmission during the BS_SIG and DN_DATA phases. At the WT, the processor is busy interpreting the packets sent by the BS during the BS_SIG and the DN_DATA phases.
E_BURST: During this phase, the WTs, which have not currently been allocated space for transmission during the UP_DATA phase, indicate whether they want to enter the WATM network. Both the WT and the BS processors are busy implementing the E_BURST phase.
The hardware design is based on the BS and each WT keeping the same timestamp values as a basis for computing the four phases of a CDF. All must maintain the same time periods in order to communicate and transfer packets effectively. All must synchronize their timestamps periodically, by copying the base station value, and all must take starting time directives from the BS.
The MAC processor is assumed to be interrupt-driven for both the WTs and the BS. The BS determines the timing for the entire system. Using the timestamp value as a reference, it determines the exact time when each of the phases operates. This timing information is sent during the BS_SIG phase. Since all phases are successive to each other, the WT and the BS set up a counter for the next phase based on the timing information, which then triggers an interrupt to the processor when the counter overflows. The processor must finish its functions during the respective phase within the time allotted and be prepared for the next phase.
For timestamp synchronization, the BS can be assumed to send a timestamp value during the BS_SIG phase. However, note that the BS is busy storing the PHY_FIFO with the packets intended for transmission during the BS_SIG and DN_DATA phases. However, the timestamp value must be determined during the BS_SIG phase and cannot be obtained during the UP_DATA phase. Consequently, the normal transmission stream must be stopped to allow for the timestamp value to be loaded from the timestamp register during the time of transmission. This solution is not desirable since it conflicts with the
Elallam Ahmed
Kizou Hassan
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