Semiconductor device manufacturing: process – Chemical etching – Vapor phase etching
Reexamination Certificate
2000-05-03
2002-11-12
Goudreau, George (Department: 1763)
Semiconductor device manufacturing: process
Chemical etching
Vapor phase etching
C438S697000, C438S700000, C438S719000, C438S720000, C438S724000
Reexamination Certificate
active
06479394
ABSTRACT:
FIELD OF THE INVENTION
This invention relates generally to semiconductor processing, and in particular, to a method of low-selective etching materials having interfaces at non-perpendicular angles to the direction of the etch propagation.
BACKGROUND OF THE INVENTION
Planarization of thin film layers in a semiconductor device and/or integrated circuit is an important aspect of semiconductor processing. Top planar surfaces are desirable for many reasons. First, subsequent formation of devices and/or structures above a surface is generally easier if the surface is planarized, as oppose to having a non-planarized topology. Second, from an operational point of view, certain devices' performance and operation improve if certain features of the devices are planarized. Third, packaging of devices and/or integrated circuits typically require a final top surface that is substantially planarized. There are other reasons for planarizing of thin film layers in semiconductor devices and/or integrated circuits.
When semiconductor processing materials are vertically stacked on top of each other in layers, the interfaces of the layers are generally horizontal. The etching of vertical stacked layers typically does not typically result an irregular surface topology since the layers are generally etched one at a time. When two or more dissimilar semiconductor processing materials are arranged in a manner that their interfaces are at non-perpendicular angles to the direction of the etch propagation, it may be difficult to achieve a substantially planarized surface after etching. This is particularly true if the dissimilar materials have substantially different etching rates.
The reason for this is that when dissimilar materials are arranged so that their interfaces are at non-perpendicular angles with respect to the etch propagation direction, the dissimilar materials are being etched at the same time. If their etching rates are different, one material will etch faster than the other material. As a result, a non-planarized topology forms since the material having the higher etching rate will have etched more than the other, and thus, would have a top surface lower than the other material.
FIG. 1
illustrates a sectional view of an exemplary semiconductor structure
100
undergoing a selective etching process. The semiconductor structure
100
may comprise a mask
102
and several dissimilar materials
104
,
106
and
108
. These materials may include, for example, a mono-crystalline silicon for material
104
, a thermal silicon oxide for material
106
, and a poly-crystalline or a silicon dioxide formed by thermal oxidation
108
. Based on a selective etching process, these materials
104
,
106
and
108
have different etching rates ER
1
, ER
2
and ER
3
, respectively.
Assume for this illustrative example that the etching rate ER
3
for the poly-crystalline or a silicon dioxide
108
is greater than the etching rate ER
1
for the mono-crystalline material
104
, and whose etching rate ER
1
is greater than the etching rate ER
2
of the thermal silicon oxide
106
. After the semiconductor structure
100
is subjected to the exemplary selective etching process, a non-planarized top surfaces of the etched materials results as illustrated in FIG.
1
. That is, because of the higher etching rate ER
3
of the thermal oxide
108
, it has a top surface that is lower than the top surface of the mono-crystalline silicon
104
which has a lower etching rate ER
1
. Similarly, because the etching rate ER
1
of the mono-crystalline silicon
104
is greater than the etching rate ER
2
of the thermal oxide
106
, the silicon
104
has a top surface that is lower than the top surface of the thermal oxide
106
. As a result, the semiconductor structure
100
has an irregular topology, which may be undesirable.
Thus, there is a need for a method of etching dissimilar materials having interfaces at non-perpendicular angles to the direction of the etch propagation that results in a low selectivity etch in order to achieve an improved planarized etched surface.
SUMMARY OF THE INVENTION
An aspect of the invention includes a method of low-selectively etching dissimilar materials having interfaces at non-perpendicular angles to the direction of the etch propagation to achieve an improved planarized etched surface. In general, the method comprises introducing a particular process gas mixture (primary factor) along with a particular process setting (secondary factor) so that the respective etching rates of the dissimilar materials are substantially the same, i.e. a substantially low-selective etching process. The etching method of the invention is particularly appropriate for etching by a plasma etch apparatus.
In a plasma etch, a primary factor affecting the etch rate of a particular material is the process gas composition. For example, hydrogen bromide (HBr) and chlorine (CL
2
) gasses typically define the etching rate of mono- and poly-crystalline silicon, whereas tri-fluoro methane (CHF
3
) and di-fluoro methane (CH
2
F
2
) typically reduces the etching rates of mono- and poly-crystalline silicon. Also, for example, CF
4
typically defmes the etching rates for oxides and nitrides, whereas oxygen (O
2
) typically reduces the etching rates of oxides and nitrides. By properly mixing of process gases, a substantially low-selective etching of dissimilar materials can be achieved.
Besides the gas composition mixture as being a primary factor in determining the etching rates for various semiconductor process materials, there are secondary factors that also affect the etching rates of these materials. For instance, the plasma power setting, the process pressure, the helium (He) pressure on the backside of the wafer, and the wafer temperature are some examples of secondary factors that can be adjusted to change the etching rate of one or more materials. Although not a primary factor in determining the etching rates of semiconductor process materials, these secondary factors can be used to “fine tune” the method of etching dissimilar materials to achieve a substantially planarized etched surface.
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A New Technique For Fabrication of OEIC's—The Etched Bac Planar Process—And Its Application To The Fabrication of Planar Embedded INP—INGAAS P-I-N-Photodiodes, by Shimizu et al., IEEE Photonics Technology Letters, IEEE Inc., New York, US, vol. 2, No. 10, Oct. 1, 1990, pp. 721-723.
Choutov Dmitri A.
Kalnitsky Alexander
Stutzin Geoffrey C.
Goudreau George
Maxim Integrated Products Inc.
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