Data processing: structural design – modeling – simulation – and em – Simulating electronic device or electrical system – Circuit simulation
Reexamination Certificate
2000-10-31
2004-04-20
Paladini, Albert W. (Department: 2125)
Data processing: structural design, modeling, simulation, and em
Simulating electronic device or electrical system
Circuit simulation
C326S104000
Reexamination Certificate
active
06725186
ABSTRACT:
FIELD OF THE INVENTION
The present invention is related to a method of logic simulation, and particularly to a method of logic simulation performed by a simulator.
BACKGROUND OF THE INVENTION
As time goes by, the electronic devices are further minimized in size. The circuits of the electronic devices thus become more and more complicated. However, the more complicated the circuit is, the higher the possibility to arise problems in logic simulation is.
Generally, logic simulation performed by a simulator is achieved by referring to the truth tables of the logic gates. From each node state of the plural nodes of a logic circuit, the final output node state of the logic circuit can be obtained by looking up the truth tables. According to the prior art, a high potential state, a low potential state and an unknown state are defined for the plural nodes of the logic circuit. In most situations, the method of logic simulation works smoothly for the logic circuit. However, a node state can't be identified in some specific situations.
Please refer to
FIG. 1
which is a schematic diagram showing a first example of a logic circuit. In real operation of the logic circuit, as long as the node state of the input node
11
and that of the input node
13
are the high potential states, the node state of the output node
17
must be the high potential state regardless of the node state of the input node
12
. However, in logic simulation performed by a simulator according to the prior art, the node state of the output node
17
can't be identified in some specific situations. By referring to Table 1 which is a truth table of a NAND gate according to the prior art, three different situations are described more specifically as follows.
TABLE 1
The first input node
The second input node
The output node
0
0
1
0
1
1
0
U
1
1
0
1
1
1
0
1
U
U
U
0
1
U
1
U
U
U
U
a) Given that the node state of the input node
11
and that of the input node
13
are the high potential states, and the node state of the input node
12
is the low potential state, then the node state of the node
14
is the high potential state, the node state of the node
15
is the high potential state and that of the node
16
is the low potential state. Therefore, the node state of the output node
17
is the high potential state.
b) Given that the node state of the input node
11
and that of the input node
13
are the high potential states, and the node state of the input node
12
is the high potential state, then the node state of the node
14
is the low potential state, the node state of the node
15
is the low potential state and that of the node
16
is the high potential state. Therefore, the node state of the output node
17
is the high potential state.
c) Given that the node state of the input node
11
and that of the input node
13
are the high potential states, and the node state of the input node
12
is the unknown state, then the node state of the node
14
is the unknown state, the node state of the node
15
is the unknown state and that of the node
16
is the unknown state. Therefore, the node state of the output node
17
is the unknown state.
Therefore, in logic simulation, the node state of the output node
17
, i.e. the unknown state, can't be identified in some situations. This kind of node state which can be determined in real operation of the logic circuit and can't be identified in some situations is called “false unknown state”.
Please refer to
FIG. 2
which is a schematic diagram showing a second example of a logic circuit. In real operation of the logic circuit, as long as the node state of the input node
11
and that of the input node
13
are the low potential states, the node state of the output node
17
must be the low potential state regardless of the node state of the input node
12
. However, in logic simulation performed by a simulator according to the prior art, the node state of the output node
17
can't be identified in some specific situations either.
In reality, the circuits for manufacturing electronic devices are much more complicated than the circuits depicted in FIG.
1
and FIG.
2
. The possibility to arise the problem of false unknown state in logic simulation is much higher.
SUMMARY OF THE INVENTION
An object of the present invention is to provide a method of logic simulation for solving the problem of false unknown state.
According to a first aspect of the present invention, a method of logic simulation comprises the steps of defining a high potential state, a low potential state, an unknown state and a fourth state for a plurality of nodes of a logic circuit, obtaining a simulating reference according to the high potential state, the low potential state, the unknown state and the fourth state, and achieving the logic simulation according to the simulating reference.
Preferably, the logic simulation is performed by a simulator.
Preferably, the fourth state is an inverse unknown state.
Preferably, the simulating reference includes a plurality of truth tables.
Preferably, the high potential state is symbolized by “1”, the low potential state is symbolized by “0”, the unknown state is symbolized by “Un” and the inverse unknown state is symbolized by “~Un”, wherein “n” represents the node number of the node.
According to a second aspect of the present invention, a simulating reference of a NAND gate, adapted to be used in logic simulation, is obtained by defining a high potential state, a low potential state, an unknown state and a fourth state for a first input node, a second input node and an output node of the NAND gate.
Preferably, the simulating reference is a truth table.
Preferably, the node number of the output node is 3, the node number of the first input node is 1 and the node number of the second input node is 2.
Preferably, the fourth state is an inverse unknown state.
Preferably, the high potential state is symbolized by “1”, the low potential state is symbolized by “0”, the unknown state is symbolized by “Un” and the inverse unknown state is symbolized by “~Un”, wherein “n” represents a node number of the node.
Preferably, the node state of the output node is “~Uy” when the node state of the first input node is “1” and that of the second input node is “Uy”.
Preferably, the node state of the output node is “1” when the node state of the first input node is “0” and that of the second input node is “Uy”. Preferably, the node state of the output node is “Uz” when the node state of the first input node is “Ux” and that of the second input node is “Uy” if x is unequal to y.
Preferably, the node state of the output node is “~Ux” when the node state of the first input node is “Ux” and that of the second input node is “Uy” if x is equal to y.
Preferably, the node state of the output node is “Uz” when the node state of the first input node is “Ux” and that of the second input node is “~Uy” if x is unequal to y.
Preferably, the node state of the output node is “1” when the node state of the first input node is “Ux” and that of the second input node is “~Uy” if x is equal to y.
According to a third aspect of the present invention, a simulating reference of a NOR gate, adapted to be used in logic simulation, is obtained by defining a high potential state, a low potential state, an unknown state and a fourth state for a first input node, a second input node and an output node of the NOR gate.
Preferably, the simulating reference is a truth table.
Preferably, the node number of the output node is 3, the node number of the first input node is 1 and the node number of the second input node is 2.
Preferably, the fourth state is an inverse unknown state.
Preferably, the high potential state is symbolized by “1”, the low potential state is symbolized by “0”, the unknown state is symbolized by “Un” and the inverse unknown state is symbolized by “~Un”, wherein “n” represents a node number of the node.
Preferably, the node state of the output node is “0” when the node state of the first input node is “1” and that of the second input node is “Uy”.
Preferably, the
Alston & Bird LLP
Paladini Albert W.
Winbond Electronics Corp.
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