Method of logic design of integrated circuit

Details Method of logic design of integrated circuit Method of logic design of integrated circuit

1988-02-08

1989-04-18

Gruber, Felix D.

Boots, shoes, and leggings

364490, G06F 1560

Patent

active

048232785

ABSTRACT:
A method for logic design of an integrated circuit IC in which at least one parameter concerning wiring line capacitances is used. The parameter can be precisely estimated even at a logic design stage preceding a layout design stage. The estimation is carried out by, first, classifying the logic units or the logic gates of the IC into hierarchal functional blocks. Second, specifying, for each closed network defined by delay paths, a higher level functional block in which the closed network is contained. Third, specifying lower level functional blocks enclosed by the higher functional block. Fourth, calculating the estimated wiring line capacitances of the closed network in accordance with predetermined data concerning both fan-out and actual wiring line capacitances. The data, used for the estimation, are varied in accordance with the degrees of the hierarchal level.

REFERENCES:
patent: 4612618 (1986-09-01), Pryor et al.
patent: 4615011 (1986-09-01), Linsker
K. C. Saraswat et al., "Effect of Scaling of Interconnections on the Tim Delay of VLSI Circuits", IEEE Journal of Solid-State Circuits, vol. SC-17, No. 2, Apr. 1982, pp. 275-280.
R. Perry et al., "Logic Design Software Casts Workstations in Role of Manufacturer's Aide", Electronic Design, vol. 32, No. 11, May 31, 1984, pp. 267-273.
D. G. Fairbairn, "VLSI: A New Frontier for Systems Designers", Computer, vol. 15, No. 1, Jan. 1982, pp. 87-96.
L. Smith, "Hierarchical Design Structures Simplify System Development", E.D.N. Electrical Design News, vol. 28, No. 19, Sep. 15, 1983, pp. 165-172.

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