Method of logic circuit simulation

Details Method of logic circuit simulation Method of logic circuit simulation

1991-06-21

1994-03-08

Trans, Vincent N.

Boots, shoes, and leggings

364488, G06F 1560, G06F 1520

Patent

active

052933270

ABSTRACT:
A method of logic simulation includes the steps of reading delay time of a logic element itself calculated in advance, converting output logic value of the logic element to a voltage value, forming a circuit equation based on connection information of an output impedance circuit of the logic element, calculating a voltage value at an arbitrary node of the output impedance circuit by solving the circuit equation, and converting a voltage value of an input node of a logic element of the succeeding stage to a logic value.

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"Signal Delay in General RC Networks with Application to Timing Simulation of Digital Integrated Circuit" by Lin et al., IEEE 1984 Conference on Advanced Research in VLSI, Jan. 1984, pp. 93-99.
"Signal Delay in RC Tree Networks" by Rubinstein et al., IEEE Trans. on Computer-Aided Design, vol. CAD-2, No. 3, Jul. 1983, pp. 202-210.
"Switch-Level Delay Model for Digital MOS VLSI" by J. K. Ousterhout, IEEE 21st Design Automation Conf., 1984, pp. 542-548.
Patel et al, "Newton: Logic Simulation With Circuit Simulation Accuracy for ASIC Design", IEEE (1986), pp. 456-459.

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