Method of linearizing ESD capacitance

Details Method of linearizing ESD capacitance Method of linearizing ESD capacitance

2008-06-03

2008-06-03

Sherry, Michael (Department: 2836)

Electricity: electrical systems and devices

Safety and protection of systems and devices

Load shunting by fault responsive means

C361S111000

Reexamination Certificate

active

07382593

ABSTRACT:
An ESD protection circuit for an input/output pad of an IC is disclosed with discharge paths to both a power rail and ground. The ESD circuit is arranged with NMOS and PMOS transistors arranged with their drains connected to the pad. However, the drain capacitances have voltage sensitivities that compensate or cancel each other, and with proper sizing the capacitance load on the pad can be made substantially constant over a given voltage range. By providing a discharge path to a power rail, the ESD circuit may be designed to be more tolerant of overvoltages on the power rail.

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