Method of leveling the laminated surface of a semiconductor subs

Details Method of leveling the laminated surface of a semiconductor subs Method of leveling the laminated surface of a semiconductor subs

1991-12-30

1993-12-21

Hearn, Brian E.

Fishing, trapping, and vermin destroying

437190, 156626, 156643, 156644, 156653, H01L 2100

Patent

active

052721159

ABSTRACT:
Disclosed is an improved method of leveling the laminated surface of a semiconductor substrate, which method permits the exact controlling of the etching of the lamination on the semiconductor substrate by detecting the sudden change of the amount of the gas resulting from the chemical reaction of the materials of the different layers with particular selected elements of surrounding plasma gas, thus assuring the reproducibility of leveled semiconductor substrate surface.

REFERENCES:
patent: 4479848 (1984-10-01), Otsubo et al.
patent: 4946550 (1990-08-01), Van Laarhoven
patent: 4965226 (1990-10-01), Gootzen et al.
patent: 4975141 (1990-12-01), Greco et al.
patent: 5169491 (1992-12-01), Doan
S. K. Ghandhi, VLSI Fabrication Principles, John Wiley and Sons, New York, 1983, pp. 504-510.
Tummala et al., ed., Microelectronics Packaging Handbook, Van Nostrand Reinhold, New York, 1989, pp. 560-565.

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