Method of layout processing including layout data verification

Details Method of layout processing including layout data verification Method of layout processing including layout data verification

1991-12-18

1993-09-28

Trans, Vincent N.

Boots, shoes, and leggings

364490, 364489, 364488, G06F 1560

Patent

active

052491340

ABSTRACT:
A method of processing layout data of an integrated circuit including several circuit blocks and inter-block routing among the circuit blocks on data verification. The method includes the steps of processing layout data within at least one of the circuit blocks and replacing the layout data within that circuit block with layout data in a peripheral neighborhood region of that circuit block to process the replaced layout data.

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