Method of laying out an integrated circuit with specific alignme

Details Method of laying out an integrated circuit with specific alignme Method of laying out an integrated circuit with specific alignme

1980-05-08

1981-06-16

Dean, R.

Metal working

Method of mechanical manufacture

Assembling or joining

29577C, 29587, 148 15, 148187, 357 20, 357 34, 357 48, 357 68, H01L 2122, H01L 21324

Patent

active

042728827

ABSTRACT:
The method entails laying out NPN transistors in a bipolar integrated circuit in a manner which prevents crystal dislocations from making the transistor unreliable. The long edges of the collector contacts are aligned in a direction substantially perpendicular to the direction between the collector contact and the emitter-base junction.

REFERENCES:
patent: 3525911 (1970-08-01), Ryerson
patent: 3539876 (1970-11-01), Feinberg et al.
patent: 3557444 (1971-01-01), Ruoff
patent: 3622842 (1971-11-01), Oberai
patent: 3874936 (1975-04-01), d'Hervilly et al.
patent: 3922707 (1975-11-01), Freed et al.
patent: 4131497 (1978-12-01), Feng et al.
patent: 4219369 (1980-08-01), Ogive et al.
Barson et al., "Gettering Technique", I.B.M. Tech. Discl. Bull., vol. 15, No. 6, Nov. 1972, p. 1752.
Murarka et al., "Study of Stacking Faults . . . Contribution to Leakage" J. Electrochem. Soc., Solid-State Sci. & Tech., Mar. 1980, pp. 716-724.

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