Method of labelling swappable pins for integrated circuit...

Details Method of labelling swappable pins for integrated circuit... Method of labelling swappable pins for integrated circuit...

2008-05-16

2011-11-01

Dinh, Paul (Department: 2825)

Computer-aided design and analysis of circuits and semiconductor

Integrated circuit design processing

C716S106000, C716S111000, C716S132000

Reexamination Certificate

active

08051395

ABSTRACT:
The present invention seeks to provide a simple, but novel regime, for re-labelling swappable pins that permits swappability information to be maintained without significantly increasing computational complexity and is conducive to inexact pattern matching for the purposes of developing more complex logical processing blocks from elementary components in design analysis. The method comprises a recursive application of a simple labelling procedure. This method is repeated recursively until all gate instances in the circuit fragment have been assigned a swappability number.

REFERENCES:
patent: 6167556 (2000-12-01), Sun et al.
patent: 6988253 (2006-01-01), Lipton et al.

Affiliated with

Also associated with

Rating

Method of labelling swappable pins for integrated circuit... does not yet have a rating. At this time, there are no reviews or comments for this patent.

If you have personal experience with Method of labelling swappable pins for integrated circuit..., we encourage you to share that experience with our LandOfFree.com community. Your opinion is very important and Method of labelling swappable pins for integrated circuit... will most certainly appreciate the feedback.

Rate now

Comments { 0 }

Profile ID: LFUS-PAI-O-4258193