Method of integration testing for packaged electronic...

Details Method of integration testing for packaged electronic... Method of integration testing for packaged electronic...

2007-01-16

2007-01-16

Le, Dung A. (Department: 2818)

Semiconductor device manufacturing: process

With measuring or testing

Packaging or treatment of packaged semiconductor

C438S011000, C438S014000, C257S048000, C257SE21524

Reexamination Certificate

active

11041980

ABSTRACT:
A method of integration testing for packaged electronic components is capable of improving a conventional testing for packaged electronic components. In this method, non-tested sides of the packaged electronic components are stuck with a downward exposure onto a testing carrier board so that conductive pins are oriented to test spaces to test the plurality of packaged electronic components stuck onto the testing carrier board according to testing steps for convenient classification packaging, advanced testing efficiency, economical working hours and costs. Programmable features and man-hour saving are provided for easy mass production and testing.

REFERENCES:
patent: 5240866 (1993-08-01), Friedman et al.
patent: 6274395 (2001-08-01), Weber

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