Method of integration of a MIM capacitor with a lower plate...

Details Method of integration of a MIM capacitor with a lower plate... Method of integration of a MIM capacitor with a lower plate...

2011-03-29

2011-03-29

Le, Dung A. (Department: 2818)

Semiconductor device manufacturing: process

Making passive device

Planar capacitor

C438S393000, C438S396000, C438S251000, C438S250000

Reexamination Certificate

active

07915134

ABSTRACT:
A MIM capacitor is formed on a semiconductor substrate having a top surface and including regions formed in the surface selected from a Shallow Trench Isolation (STI) region and a doped well having exterior surfaces coplanar with the semiconductor substrate. A capacitor lower plate is either a lower electrode formed on the STI region in the semiconductor substrate or a lower electrode formed by a doped well formed in the top surface of the semiconductor substrate that may have a silicide surface. A capacitor HiK dielectric layer is formed on or above the lower plate. A capacitor second plate is formed on the HiK dielectric layer above the capacitor lower plate. A dual capacitor structure with a top plate may be formed above the second plate with vias connected to the lower plate protected from the second plate by side wall spacers.

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