Semiconductor device manufacturing: process – Making device or circuit responsive to nonelectrical signal
Reexamination Certificate
2003-04-18
2004-09-28
Tsai, H. Jey (Department: 2812)
Semiconductor device manufacturing: process
Making device or circuit responsive to nonelectrical signal
C438S050000, C438S637000
Reexamination Certificate
active
06797534
ABSTRACT:
DESCRIPTION OF THE INVENTION
1. Field of the Invention
This invention pertains in general to a fabrication process of a micro-electromechanical (“MEM”) device. More particularly, this invention relates to methods of integrating the fabrication processes of MEM devices and integrated circuits.
2. Background of the Invention
MEM devices have many known applications in microactuators and microsensors. A fabrication process that combines those of MEM devices and microelectronic circuits in a modular fashion is advantageous from the perspective of system performance and cost. To make the fabrication of MEM devices compatible with a typical complementary metal-oxide-semiconductor (“CMOS”) process, however, conventional techniques require separate processes for fabricating MEM devices and integrated circuits. For example, integrated circuits are usually fabricated prior to starting the MEM fabrication process. Such a fabrication strategy is disadvantageous in that some processing steps common to the integrated circuits and MEM devices, including, for instance, depositing dielectric layers, etching via holes and forming metal layers, are repeatedly performed in separate processes, resulting in an increase in fabrication cost.
SUMMARY OF THE INVENTION
Accordingly, the present invention is directed to a fabrication process that obviates one or more of the problems due to limitations and disadvantages of the related art.
Additional features and advantages of the invention will be set forth in the description which follows, and in part will be apparent from the description, or may be learned by practice of the invention. The objectives and other advantages of the invention will be realized and attained by the circuit structures particularly pointed out in the written description and claims thereof, as well as the appended drawings.
To achieve these and other advantages, and in accordance with the purpose of the invention as embodied and broadly described, there is provided a method of forming a MEM device with an integrated circuit that includes providing a semiconductor substrate including a first region and a second region, forming an integrated circuit device on the first region, forming a first insulating layer on the semiconductor substrate, etching the first insulating layer to form a first dielectric layer on the first region and a second dielectric layer on the second region spaced apart from the first dielectric layer, forming a second insulating layer over the semiconductor substrate, the first dielectric layer and the second dielectric layer, etching the second insulating layer to expose the first dielectric layer, forming a third insulating layer over the semiconductor substrate, the second insulating layer and the first dielectric layer, etching the third insulating layer to form a plurality of vias, and forming a metal layer over the semiconductor substrate to fill the vias.
In one aspect, the first insulating layer is composed of borophosphosilicate glass.
In another aspect, the first insulating layer has a thickness in the range of approximately 6500~11000 Å.
Also in accordance with the present invention, there is provided a method of integrating a fabrication process of a MEM device with a fabrication process of an integrated circuit that includes forming an integrated circuit device on a semiconductor substrate, forming a borophosphosilicate glass layer on the semiconductor substrate, etching the borophosphosilicate glass layer to form a first dielectric layer over a first region in the semiconductor substrate and a second dielectric layer on a second region in the semiconductor substrate, wherein the second dielectric layer is spaced apart from the first dielectric layer, forming a first insulating layer over the semiconductor substrate, the first dielectric layer and the second dielectric layer, forming a conductive film on the first insulating layer, etching the first insulating layer and the conductive film to expose the first dielectric layer, forming a second insulating layer over the semiconductor substrate, the first insulating layer and the first dielectric layer, etching the second insulating layer to form a plurality of vias, and forming a metal layer over the semiconductor substrate to fill the vias.
It is to be understood that both the foregoing general description and the following detailed description are exemplary and explanatory and are intended to provide further explanation of the invention as claimed.
REFERENCES:
patent: 2003/0186480 (2003-10-01), Okumura et al.
Chiang Lu-Shan
Chu Shih-Lin
Tu Shuo-Lin
Finnegan Henderson Farabow Garrett & Dunner L.L.P.
Macronix International Co. Ltd.
Tsai H. Jey
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