Metal working – Method of mechanical manufacture – Assembling or joining
Patent
1983-04-22
1985-01-29
Roy, Upendra
Metal working
Method of mechanical manufacture
Assembling or joining
29576B, 148 15, 148187, 357 23, 357 91, G11C 1140, B01J 1700, H01L 2927
Patent
active
044956932
ABSTRACT:
A nonvolatile semiconductor memory device is provided having a MOS transistor and a floating gate type MOS transistor. The length of an overlap between a floating gate and a drain region of the floating gate type MOS transistor is made smaller than that of an overlap between the gate and the drain region of the MOS transistor.
REFERENCES:
patent: 3868187 (1975-02-01), Masouka
patent: 3984822 (1976-10-01), Simko et al.
patent: 4122544 (1978-10-01), McElroy
patent: 4128773 (1978-12-01), Troutman et al.
patent: 4142926 (1979-03-01), Morgan
patent: 4203158 (1980-05-01), Bentchowsky et al.
patent: 4247918 (1981-01-01), Iwahashi et al.
patent: 4258378 (1981-03-01), Wall
patent: 4278989 (1981-07-01), Baba et al.
patent: 4288256 (1981-09-01), Ning et al.
patent: 4292728 (1981-10-01), Endo
patent: 4302766 (1981-11-01), Guterman et al.
patent: 4330850 (1982-05-01), Jacobs et al.
patent: 4355455 (1982-10-01), Boettcher
patent: 4409723 (1983-10-01), Harari
Asano Masamichi
Iwahashi Hiroshi
Mito Masazi
Yoskikawa Kuniyoshi
Roy Upendra
Tokyo Shibaura Denki Kabushiki Kaisha
LandOfFree
Method of integrating MOS devices of double and single gate stru does not yet have a rating. At this time, there are no reviews or comments for this patent.
If you have personal experience with Method of integrating MOS devices of double and single gate stru, we encourage you to share that experience with our LandOfFree.com community. Your opinion is very important and Method of integrating MOS devices of double and single gate stru will most certainly appreciate the feedback.
Profile ID: LFUS-PAI-O-499415