Method of integrated circuit manufacturing including cell assemb

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430311, 430319, 430320, G03C 500

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052292312

ABSTRACT:
A method is described which reduces the size of the constraint graph used in assembling cells into a tiled module for integrated circuit manufacture. The smaller size significantly reduces the amount of time required to assemble the cells appropriately.

REFERENCES:
28th ACM/IEEE Design Automation Conferences; Tsay et al.; paper 37.2; "An Analytical Net Weighing Approach for Performance Optimization in Circuit Placement"; 1991.
28th ACM/IEEE Design Automation Conferences; Harrison; paper 41.4; "VLSI Layout Compaction Using Radix Priority Search Trees"; 1991.
28th ACM/IEEE Design Automation Conferences; Dutt et al.; paper 41.5; "On Minimal Closure Constraint Geneation for Symbolic Cell Assembly"; 1991.
IEEE International Conference on Computer-Aided Design; Reichelt et al., pp. 482-485; "An Improved Cell Model for Hierarchial Constraint-Graph Compaction"; 1986.

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