Method of integrated circuit fabrication having planarized diele

Details Method of integrated circuit fabrication having planarized diele Method of integrated circuit fabrication having planarized diele

1992-11-12

1993-12-07

Chaudhuri, Olik

Fishing, trapping, and vermin destroying

437194, 437235, 437947, 437981, 156644, H01L 21465

Patent

active

052683320

ABSTRACT:
A method for forming an integrated circuit with a planarized dielectric is disclosed. Runners and gates are covered with a protective dielectric layer. Then a conventional dielectric is deposited and planarized over the entire circuit surface. When windows are opened to runners and to source/drain regions, the protective dielectric helps to slow the etch process over the runner, thus protecting the runner from damage during the extra time required for the etch process to reach the source or drain.

REFERENCES:
patent: 4814041 (1989-03-01), Auda
patent: 5022958 (1991-06-01), Favreau et al.

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