Method of integrated circuit chips design

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364491, G06F 1560

Patent

active

053474651

ABSTRACT:
An automated, custom personalization process for generating integrated gate array chips is defined which enhances yield and reliability potential. Unused data provided in the general purpose design is deleted through a selective detection procedure based on circuit utilization.

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IBM Technical Disclosure Bulletin, Selective Removal of Polysilicon To Obtain Improved Masterslice, vol. 31, Sep. 1988.

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