Method of inspection of semiconductor memory device

Details Method of inspection of semiconductor memory device Method of inspection of semiconductor memory device

1974-10-15

1976-06-08

Fears, Terrell W.

Communications: electrical

Digital comparator systems

340173BB, 3401725, G11C 1300

Patent

active

039626873

ABSTRACT:
In a method of inspection of a semiconductor memory device, selection signals for selecting a memory cell to be tested and a designation signal for designating the address of a predetermined memory cell are compared, to produce a mask instruction signal when the address of the memory cell to be tested is coincident with the address of the predetermined memory cell, and the judgment of the test result of the predetermined memory cell is masked by the mask instruction signal. If the predetermined memory cell is one known to be inferior during the wiring check, it will be also defection during the test of any characteristic. Since such memory cells with inferior wiring are masked in characteristic tests, the analysis of defects is facilitated.

REFERENCES:
patent: 3222653 (1965-12-01), Rice
patent: 3336579 (1967-08-01), Heyman
patent: 3541525 (1970-11-01), Gange
patent: 3633268 (1972-01-01), Engbert
patent: 3800294 (1974-03-01), Lawlor
patent: 3813650 (1974-05-01), Hunter

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